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| INTEGRATED CIRCUITS DATA SHEET TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Preliminary specification Supersedes data of 2003 Oct 06 2003 Dec 16 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver FEATURES General * A-rabitteTM(1): supports any bit rate from 30 Mbit/s to 3.2 Gbit/s with one single reference frequency * 4-bit parallel interface * Selectable Double Data Rate (DDR, half clock rate) or Single Data Rate (SDR) clocking scheme on parallel interface, enabling easy interfacing with FPGA devices * I2C-bus and pin programmable * Six selectable reference frequency ranges * Transmitter, receiver and transceiver modes * Clean-up loop back mode * Line loop back mode * Diagnostic loop back mode * Serial loop timing mode * Single 3.3 V power supply. Limiter * Limiting amplifier with typical 5 mV input sensitivity * Received Signal Strength Indicator (RSSI) * Loss Of Signal (LOS) indicator with adjustable threshold * Differential overvoltage protection. Data and clock recovery and synthesizer * Supports any bit rate from 30 Mbit/s to 3.2 Gbit/s when using I2C-bus interface * Supports eight pre-programmed (pin selectable) bit rates: - SDH/SONET rates at 155.52 Mbit/s, 622.08 Mbit/s, 2488.32 Mbit/s and 2666.06 Mbit/s (STM16/OC48 + FEC) - Gigabit Ethernet at 1250 Mbit/s and 3125 Mbit/s - Fibre Channel at 1062.5 Mbit/s and 2125 Mbit/s. * Provides stable clock signal at LOS * Frequency lock indicator for DCR * Loss Of Lock (LOL) indicator for synthesizer * ITU-T compliant jitter tolerance for Data and Clock Recovery (DCR) * ITU-T compliant jitter transfer for DCR in clean-up loop back mode * ITU-T compliant jitter generation for synthesizer. Multiplexer * 4 : 1 multiplexing ratio TZA3015HW * Supports co-directional and contra-directional clocking * 4-stage FIFO for wide tolerance to clock skew * Rail-to-rail parallel inputs compliant with LVPECL, Current-Mode Logic (CML) and LVDS * Programmable parity checking * CML data and clock outputs. Demultiplexer * 1 : 4 demultiplexing ratio * Adjustable LVDS output swing * Frame detection for SDH/SONET and Gigabit Ethernet (GE) frames. I2C-bus configurable options * Programmable frequency resolution of 10 Hz * Independent receive and transmit bit rate * Slice level adjustment to improve Bit Error Rate (BER) * Six reference frequency ranges * Adjustable swing for CML serial data and clock outputs * Programmable polarity of RF I/Os * Clock versus data swap for optimum connectivity * Swap of parallel bus for optimum connectivity * Mute function for a forced logic 0 output state * Programmable parity * Programmable 32-bit frame detection. (1) A-rate is a trademark of Koninklijke Philips Electronics N.V. 2003 Dec 16 2 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver APPLICATIONS * Any optical transmission system with line rates between 30 Mbit/s and 3.2 Gbit/s * Physical interface IC in receive and transmit channels * Transponder applications * Dense wavelength division multiplexing systems * Due to DDR clocking option, the ultimate physical interface for FPGA based designs. GENERAL DESCRIPTION TZA3015HW The TZA3015HW is a fully integrated optical network transceiver containing a limiter, data and clock recovery circuit, clock synthesizer, 1 : 4 demultiplexer and 4 : 1 multiplexer. The A-rate feature allows the IC to operate at any bit rate between 30 Mbit/s and 3.2 Gbit/s with one single reference frequency. All clock signals are generated using a fractional N synthesizer with 10 Hz resolution offering a true continuous rate operating. For full configuration flexibility the transceiver can be programmed by pin and via the I2C-bus. ORDERING INFORMATION TYPE NUMBER TZA3015HW PACKAGE NAME HTQFP100 DESCRIPTION plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad VERSION SOT638-1 2003 Dec 16 3 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver BLOCK DIAGRAM CREF FIFORESET TZA3015HW PAREVEN TXPRSCL/ TXPRSCLQ LOL 89, 90 91 OVERFLOW 81 82 83 CREFQ 93 94 TXPCO/ TXPCOQ ENDDR 79, 80 45 TXPARERR/ TXPARERRQ 86, 87 FREF0 FREF1 ENRX ENTX LM0 LM1 LM2 TXSD TXSDQ TXSC TXSCQ ENTXSC 42 95 31 32 27 28 29 5 6 9 10 3 BUF BUF LOOP MODE SELECT /R CLOCK SYNTHESIZER PHASE SHIFT 64 65 CLK MUX 88 TXPC/ TXPCQ CLKDIR TXPAR/ TXPARQ TXPD3/ TXPD3Q TXPD2/ TXPD2Q TXPD1/ TXPD1Q TXPD0/ TXPD0Q RXPAR/ RXPARQ RXPD3/ RXPD3Q RXPD2/ RXPD2Q RXPD1/ RXPD1Q RXPD0/ RXPD0Q RXPC/ RXPCQ RXFP/ RXFPQ ENBA /4 LM MUX 76 77 PARITY CHECK AND BUS SWAP MUX 4:1 FIFO 69 70 67 68 48 49 PARITY GENERATOR AND BUS SWAP DMX 1:4 61 62 59 60 57 58 55 56 73 74 71 72 c LOOP d d MUX c RXSD RXSDQ 16 17 LIM DLB MUX PHASE DETECTOR RSSI RSSI LOSTH 20 19 LOS FREQUENCY WINDOW DETECTOR LPF VCO ENDDR 52 53 46 47 43 TZA3015HW RREF LOS SCL(DR2) SDA(DR1) CS(DR0) UI 14 21 24 23 22 13 25 VDD I2C-BUS CLEAN-UP PLL INTERRUPT CONTROLLER 15, 18, 92 VCCA 41 LOWSWING (1) (2) 96 IPUMP 98, 99 38 37 1, 34 VCCO 30 INT mgu679 VEE VCCD INWINDOW WINSIZE RXPRSCL/ RXPRSCLQ (1) Connected to pins 2, 12, 26, 33, 35, 40, 50, 84 and 100. (2) Connected to pins 4, 7, 8, 11, 36, 39, 44, 51, 54, 63, 66, 75, 78, 85 and 97. Fig.1 Block diagram. 2003 Dec 16 4 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver PINNING SYMBOL VEE VCCO VEE ENTXSC VCCD TXSD TXSDQ VCCD VCCD TXSC TXSCQ VCCD VEE UI RREF VCCA RXSD RXSDQ VCCA LOSTH RSSI LOS CS(DR0) SDA(DR1) SCL(DR2) VDD VEE LM0 LM1 LM2 INT ENRX ENTX VEE VCCO VEE 2003 Dec 16 PIN die pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 DESCRIPTION common ground plane supply voltage (clock generator) ground enable serial clock digital supply voltage serial data output serial data output inverted supply voltage (digital part) supply voltage (digital part) serial clock output serial clock output inverted supply voltage (digital part) ground user interface select input reference resistor input supply voltage (analog part) serial data input serial data input inverted supply voltage (analog part) loss of signal threshold input received signal strength indicator output loss of signal output chip select output (data rate select input 0) I2C-bus serial data input and output (data rate select input 1) I2C-bus serial clock input (data rate select input 2) supply voltage (digital) ground loop mode select input 0 loop mode select input 1 loop mode select input 2 interrupt output enable receiver enable transmitter ground supply voltage (clock generator) ground 5 ENBA VCCD ENDDR RXFP RXFPQ RXPAR RXPARQ VEE VCCD RXPC RXPCQ VCCD RXPD0 RXPD0Q RXPD1 RXPD1Q RXPD2 RXPD2Q RXPD3 RXPD3Q VCCD TXPC TXPCQ VCCD TXPD0 TXPD0Q TXPD1 TXPD1Q TXPD2 TXPD2Q TXPD3 TXPD3Q 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 SYMBOL VCCD WINSIZE INWINDOW VCCD VEE LOWSWING FREF0 PIN 36 37 38 39 40 41 42 TZA3015HW DESCRIPTION supply voltage (digital part) wide and narrow frequency detect window select input frequency window detector output supply voltage (digital part) ground enable low LVDS swing reference frequency select input 0 enable byte alignment supply voltage (digital part) enable DDR frame pulse output frame pulse output inverted parity output parity output inverted ground supply voltage (digital part) parallel clock output parallel clock output inverted digital supply voltage parallel data output 0 parallel data output 0 inverted parallel data output 1 parallel data output 1 inverted parallel data output 2 parallel data output 2 inverted parallel data output 3 parallel data output 3 inverted supply voltage (digital part) parallel clock input parallel clock input inverted supply voltage (digital part) parallel data input 0 parallel data input 0 inverted parallel data input 1 parallel data input 1 inverted parallel data input 2 parallel data input 2 inverted parallel data input 3 parallel data input 3 inverted Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver SYMBOL VCCD TXPAR TXPARQ VCCD TXPCO TXPCOQ PAREVEN OVERFLOW FIFORESET VEE VCCD TXPARERR TXPARERRQ CLKDIR PIN 75 76 77 78 79 80 81 82 83 84 85 86 87 88 DESCRIPTION supply voltage (digital part) parity input parity input inverted supply voltage (digital part) transmitter parallel clock output transmitter parallel clock output inverted parity select input (odd or even) FIFO overflow alarm output FIFO reset input ground supply voltage (digital part) parity error output parity error output inverted selection input between co- and contra-directional clocking VCCD RXPRSCL RXPRSCLQ VEE 97 98 99 100 IPUMP 96 LOL VCCA CREF CREFQ FREF1 91 92 93 94 95 SYMBOL TXPRSCL TXPRSCLQ PIN 89 90 TZA3015HW DESCRIPTION prescaler synthesizer output prescaler synthesizer output inverted loss of lock output supply voltage (analog part) reference clock input reference clock input inverted reference frequency select input 1 clean-up PLL charge pump output supply voltage (digital part) prescaler DCR output prescaler DCR output inverted ground 2003 Dec 16 6 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW 87 TXPARERRQ 81 PAREVEN 98 RXPRSCL 89 TXPRSCL 80 TXPCOQ handbook, full pagewidth 82 OVERFLOW 83 FIFORESET 99 RXPRSCLQ 86 TXPARERR 90 TXPRSCLQ 78 VCCD 77 TXPARQ 88 CLKDIR 94 CREFQ 79 TXPCO VCCO VEE ENTXSC VCCD TXSD TXSDQ VCCD VCCD TXSC 100 VEE 76 TXPAR 75 VCCD 74 TXPD3Q 73 TXPD3 72 TXPD2Q 71 TXPD2 70 TXPD1Q 69 TXPD1 68 TXPD0Q 67 TXPD0 66 VCCD 65 TXPCQ 64 TXPC 63 VCCD 62 RXPD3Q 61 RXPD3 60 RXPD2Q 59 RXPD2 58 RXPD1Q 57 RXPD1 56 RXPD0Q 55 RXPD0 54 VCCD 53 RXPCQ 52 RXPC 51 VCCD 95 FREF1 96 IPUMP 97 VCCD 1 2 3 4 5 6 7 8 9 TXSCQ 10 VCCD 11 VEE 12 UI 13 RREF 14 VCCA 15 RXSD 16 RXSDQ 17 VCCA 18 LOSTH 19 RSSI 20 LOS 21 CS(DR0) 22 SDA(DR1) 23 SCL(DR2) 24 VDD 25 TZA3015HW VEE 26 LM0 27 LM1 28 LM2 29 INT 30 ENRX 31 ENTX 32 VEE 33 VCCO 34 VEE 35 VCCD 36 WINSIZE 37 INWINDOW 38 VCCD 39 VEE 40 LOWSWING 41 FREF0 42 85 VCCD 84 VEE 92 VCCA 91 LOL 93 CREF ENBA 43 VCCD 44 ENDDR 45 RXFP 46 RXFPQ 47 RXPAR 48 RXPARQ 49 VEE 50 MGU680 Fig.2 Pin configuration. 2003 Dec 16 7 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver FUNCTIONAL DESCRIPTION The TZA3015HW contains the following main blocks: * General part: configuration via I2C-bus mode or pre-programmed mode * Receiver part: limiting amplifier, data and clock recovery and demultiplexer * Transmitter part: clock synthesizer and multiplexer. General CONFIGURATION The IC features two types of user interface: I2C-bus or direct pin programming of eight predefined modes. The mode selection is set by pin UI. The I2C-bus mode is operational and A-rate functionality is enabled if pin UI is left open-circuit or connected to VCC (see Table 1). If pin UI is connected to VEE, the eight pre-programmed modes can be selected with pins CS(DR0), SDA(DR1) and SCL(DR2). Table 1 UI LOW HIGH Truth table for pin UI MODE pre-programmed I2C-bus PIN 22 DR0 CS PIN 23 DR1 SDA PIN 24 DR2 SCL TZA3015HW Some functions of the TZA3015HW can be controlled both using pre-program mode and via the I2C-bus. In these cases, an extra I2C-bus bit called I2C I2C-BUS MODE In I2C-bus mode the IC can be configured by using pins SDA and SCL. Pin CS has to be HIGH during the I2C-bus read or write actions. When pin CS is made LOW, the programmed configuration remains active, but signals SDA and SCL are ignored. In this way, all ICs in the application with the same I2C-bus address (e.g. other TZA3015HWs) are individually accessible. The I2C-bus address is given in Table 2. Table 2 Device address of the TZA3015HW DEVICE ADDRESS BITS A6 1 A5 0 A4 1 A3 0 A2 1 A1 0 A0 0 X * Loss of lock detection (LOL) * FIFO overflow indication (OVERFLOW) * FIFO reset (FIFORESET) * Supported reference frequencies: 19.44, 38.88, 155.52 and 622.08 MHz. After power-up, the TZA3015HW initiates a Power-On Reset (POR) sequence to restore the default settings of the I2C-bus registers, regardless of the user interface. See Table 21 for the defaults and a detailed list of all I2C-bus registers and the meaning of their contents. 2003 Dec 16 8 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 3 DR2 LOW LOW LOW LOW HIGH HIGH HIGH HIGH Truth table for pins DR2 to DR0 (pin UI = VEE) DR1 LOW LOW HIGH HIGH LOW LOW HIGH HIGH DR0 LOW HIGH LOW HIGH LOW HIGH LOW HIGH PROTOCOL STM1/OC3 STM4/OC12 STM16/OC48 GE 10GE BIT RATE (Mbit/s) 155.52 622.08 2488.32 1250.00 3125.00 INQ handbook, halfpage TZA3015HW VCCA IN 50 STM16 + FEC 2666.06 50 Fibre Channel 1062.50 Fibre Channel 2125.00 VEE MDB385 Receiver LIMITING AMPLIFIER The TZA3015HW contains a limiting amplifier (see Fig.3). To achieve optimum receiver sensitivity for any bit rate, the bandwidth of the amplifier is automatically scaled with the bit rate. Wideband noise of the optical front-end (photo detector and transimpedance amplifier) is thus reduced for lower bit rates. When using the I2C-bus, the bandwidth of the amplifier can be set independently of the bit rate with bits AMP[2:0] in register LIMCON (D3h). The highest bandwidth is selected as default at power-up. Fig.3 Limiter input termination configuration. Received Signal Strength Indicator (RSSI) The signal strength at the input is measured with a logarithmic detector. The logarithmic detector converts the input signal amplitude into a voltage which can be measured at pin RSSI. The RSSI reading has a dynamic range of 40 dB with a sensitivity (SRSSI) of 17 mV/dB (typical) for a Vi(p-p) range of 5 to 500 mV (see Fig.4). VRSSI can be calculated using the following formula: V i(p-p) V RSSI = V RSSI(32mV) + S RSSI x 20log ---------------32 mV where: VRSSI(32mV) = 680 mV (typical). handbook, full pagewidth MCE412 1.2 VRSSI (V) 0.9 SRSSI 0.68 0.6 0.3 0 5 10 32 102 300 500 103 Vi(p-p) (mV) Fig.4 VRSSI as a function of Vi(p-p). 2003 Dec 16 9 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Loss Of Signal (LOS) indicator Besides the analog RSSI output, a digital LOS indication is present on the TZA3015HW. The RSSI level is internally compared with a LOS threshold, which can be set by connecting an external resistor to pin LOSTH or by means of an internal DAC which is accessible via the I2C-bus. TZA3015HW VCCA RSSI Bit I2CLOSTH of register LIMLOSCON (D1h) enables the 8-bit DAC, of which the value needs to be programmed into register LIMLOSTH (D0h). The threshold level is adjustable in 256 steps from 0 to 1.2 V. If the received signal strength is below the threshold value, pin LOS will be HIGH. A default hysteresis of 3 dB is applied in the comparator. The hysteresis can be set with bits HTLC[2:0] in register LIMLOSCON (D1h). The programmable range is 0 to 7 dB. The polarity of the LOS output can be inverted by bit LOSPOL of register LIMLOSCON (D1h) to provide more flexibility in the application. Fig.5 1.2 V Vref VEE I RREF R1 10 k LOS compare LOSTH R2 RSSI LOS ground MGU681 LOSTH reference setting by external resistor If the built-in DAC is not used, the reference voltage level to pin LOSTH can be set by connecting an external resistor (R2) between pin LOSTH and ground. VLOSTH is determined by the resistor ratio between R2 and R1 (see Fig.5). For resistor R1 a value of 10 to 20 k is recommended, yielding a current of 120 to 60 A through R1. R2 VLOSTH = ------ x V ref R1 Vref represents a temperature stabilized and accurate reference voltage of 1.2 V. The minimum threshold level corresponds to 0 V and the maximum to 1.2 V. Hence, the value of R2 may not be higher than R1. The accuracy of VLOSTH depends mainly on the matching of the two external resistors. Apart from using resistors (R1 and R2) to set the LOS threshold, an accurate external voltage source may also be used. If no resistor is connected or an external voltage higher than 2/3 x VCC is applied to pin LOSTH, the LOS detection circuit (including the RSSI reading) is automatically switched off to reduce power dissipation. This `auto power off' function only works in the pre-programmed mode. I2C-bus mode allows flexible configuration. Setting the LOSTH reference level by external resistors. Slice level adjustment Due to asymmetrical noise in some optical transmission systems, a pre-detection signal-to-noise ratio improvement can be achieved by adding a DC offset to the input signal. This is done by the slice level circuit in the TZA3015HW. The required offset depends on the photo detector characteristics in the optical front-end and the amplitude of the received signal. The slice level is adjustable between -50 and +50 mV in 512 steps of 0.2 mV. Bit SLEN of register LIMLOSCON (D1h) enables the slice function. The slice level is set by sign and magnitude convention. The polarity sign is set by bit SLSGN in register LIMLOSCON (D1h). The magnitude is set by an 8-bit DAC, accessible via register LIMSL (D2h), from 0 to 50 mV in 256 steps. The introduced offset is not present on input pins RXSD(Q), in order not to affect the logarithmic RSSI detector, which would detect the offset as a valid input signal. 2003 Dec 16 10 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver DATA AND CLOCK RECOVERY (DCR) The TZA3015HW recovers the clock and data contents from the incoming bit stream; see Fig.6. The DCR uses a combined frequency and phase locking scheme, providing reliable and quick data acquisition on any bit rate between 30 Mbit/s and 3.2 Gbit/s. At power-up, coarse adjustment of the free running Voltage Controlled Oscillator (VCO) frequency is required. This is achieved by the Frequency Window Detector (FWD) circuit. The FWD is a conventional frequency locked PLL. The FWD checks the VCO frequency, which has to be within a 1000 ppm window around the required frequency. The FWD then compares the divided VCO frequency, also available on pins RXPRSCL(Q), with the reference frequency on pins CREF(Q), usually 19.44 MHz. If the VCO frequency is outside this window, the FWD disables the Data Phase Detector (DPD) and forces the VCO to a frequency within the window. As soon as the `in window' condition occurs, which is visible on pin INWINDOW, the DPD is enabled and will lock on the incoming bit stream. Since the VCO frequency is very close to the expected bit rate, the phase acquisition will be almost instantaneous, resulting in quick phase lock to the incoming data stream. Although the VCO is now locked to the incoming bit stream, the FWD is still supervising the VCO frequency TZA3015HW and takes over control if the VCO frequency drifts outside the predefined frequency window. This might occur during a `loss of signal' situation. Due to the FWD, the VCO frequency is always close to the required bit rate, enabling rapid phase acquisition when the lost input signal returns. Due to the loose coupling of 1000 ppm, the reference frequency does not need to be highly accurate or stable. Any crystal-based oscillator that generates a reasonably accurate frequency (e.g. 100 ppm) will do. This only holds if the TZA3015HW is used as a receiver since the synthesizer of the transmitter uses the same reference clock. The transmitter does need a very accurate reference frequency. Fractional N synthesizer in the DCR The DCR section contains a fractional N synthesizer as frequency acquisition aid for the A-rate functionality. This allows the DCR to synchronize on incoming data, regardless of the received bit rate. Any combination of bit rate and reference frequency is possible, due to the 22 bits fractional N synthesizer, allowing approximately 10 Hz frequency resolution. The LSB (bit K0) should be set to logic 1 to avoid limit cycles (cycles of less than maximum length). This leaves 21 bits (bits K[21:1]), available for free programming. handbook, full pagewidth recovered data from limiting amplifier and DLB MUX OCTAVE DIVIDER recovered clock DATA PHASE DETECTOR /M VOLTAGE CONTROLLED OSCILLATOR MAIN Frac DIVIDER N, K /N REFERENCE DIVIDER divided CREF(Q) up FREQUENCY WINDOW DETECTOR down CHARGE PUMP up down CHARGE PUMP to demultiplexer LOOP FILTER + RXPRSCL(Q) PRESCALER BUFFER MGU683 INWINDOW WINSIZE Fig.6 Functional diagram of data and clock recovery. 2003 Dec 16 11 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver DCR programming Programming the DCR involves four dividers: * Reference divider R * Main divider N * Fractional divider K * Octave divider M. The first step is to determine in which octave the desired bit rate fits, see Fig.7 and Tables 4 and 5. Figure 7 shows the position of the most commonly used line rates in relation to the defined octaves of the TZA3015HW. Table 5 lists the most commonly used standards together with the associated line rates. Table 4 clarifies the octave definitions. This yields the value for the octave divider M. The value for R is determined by the reference frequency and the received bit rate (see Section "Reference clock programming"). 10GE 2xHDTV STM16/OC48 + FEC STM16/OC48 DV-6000 Fibre Channel HDTV D-1 video DV-6010 Gigabit Ethernet Fibre Channel OptiConnect ISC STM4/OC12 handbook, 6 halfpage 5 TZA3015HW Table 5 Most-common optical transmission protocols BIT RATE (Mbit/s) 3125.00 2970.00 2666.06 2488.32 2380.00 2125.00 1485.00 1380.00 1300.00 1250.00 1062.50 1062.50 1062.50 622.08 595.00 425.00 265.63 212.50 200.00 155.52 125.00 125.00 106.25 51.84 OCTAVE 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 3 3 4 4 4 4 4 5 6 PROTOCOL 4 3 2 1 0 DV-6400 Fibre Channel OptiConnect Fibre Channel ESCON/SBCON STM1/OC3 FDDI 28.125 56.25 112.5 225 450 900 1800 3200 Mbits/s MGU316 Fast Ethernet Fibre Channel OC1 Fig.7 Commonly used line rates and allocation of octaves along a logarithmic bit rate scale. Table 4 Octave definition M 1 2 4 8 16 32 64 LOWEST BIT RATE (Mbit/s) 1800 900 450 225 112.5 56.25 28.125 HIGHEST BIT RATE (Mbit/s) 3200 1800 900 450 225 112.5 56.25 The values for N and K are derived from the division ratio (n.k). The division ratio (n.k) can be calculated with the following formula: bit rate x M x R n.k = --------------------------------------f ref where: n = integer part of the division ratio k = fractional part of the division ratio bit rate = bit rate at serial input in Mbit/s M = octave divider M R = reference divider R fref = reference frequency in MHz. OCTAVE 0 1 2 3 4 5 6 2003 Dec 16 12 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth CALCULATE N and K n.k = bit rate x M x R fref n is integer part k is fractional part yes k=0? no RXNILFRAC = 1 RXNILFRAC = 0 no k 0.25 ? yes no k 0.75 ? yes k = k + 0.5 k = k - 0.5 N=2xn+1 no 0.25 < k < 0.75 yes N=2xn N=2xn N=2xn-1 j = 21 k=kx2 no k1? yes Kj = 1 k=k-1 Kj = 0 decimal to binary conversion of fractional part j=j-1 no j=0? yes K0 = 1 Write Kj into registers C3h, C4h, C5h or E3h, E4h, E5h Convert N to binary and write into registers C1h, C2h or E1h, E2h END MCE413 Fig.8 Flowchart for calculating N and K. 2003 Dec 16 13 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW Having calculated the division factor (n.k), the values for N and K can be calculated according to the flow depicted in the flowchart of Fig.8. The value of the octave divider M is programmed by bits RXDIV_M[2:0] in register RXOCTDIV (C0h). The value for the main divider N is programmed by bits RXN[8:0] in registers RXMAINDIV1 (C1h) and RXMAINDIV0 (C2h). The value for the fractional divider K is programmed by bits RXK[21:0] in registers RXFRACN2 to RXFRACN0 (C3h to C5h). Bit RXNILFRAC in register RXFRACN2 (C3h) must be set depending on whether there is a fractional part or not. Example 1: An SDH or SONET link has a bit rate of 2488.32 Mbit/s (STM16/OC48) and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 77.76 MHz. This means that the reference division R needs to be 4. The values of n and k can be calculated from the flowchart: bit rate x M x R 2488.32 Mbits x 1 x 4 n.k = --------------------------------------- = -------------------------------------------------------- = 128 f ref 77.76 MHz Since k = 0 in this example, no fractional functionality is required, bit RXNILFRAC (register C3h), should be logic 1. N = 2 x n and no correction is required. Consequently the appropriate values are: R = 4 (register A1h), M = 1 (register C0h) and N = 256 (registers C1h and C2h). Example 2: An SDH STM16 or SONET OC48 link with FEC has a bit rate of 2666.057143 Mbit/s (15/14 x 2488.32 Mbit/s) and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 38.88 MHz. This means that the reference division R needs to be 2. The values of n and k can be bit rate x M x R 2666.05714283 Mbits x 1 x 2 calculated from the flowchart: n.k = --------------------------------------- = ---------------------------------------------------------------------------- = 137.1428571 f ref 38.88 MHz This means that n = 137, k = 0.1428571 and bit RXNILFRAC (register C3h) should be logic 0. Since k < 0.25, k is corrected to 0.6428571, while the corrected N becomes N = 273. Consequently the appropriate values are: R = 2 (register A1h), M = 1 (register C0h), N = 273 (registers C1h and C2h) and K = 10 1001 0010 0100 1001 0011 (registers C3h to C5h). The FEC bit rate is usually quoted to be 2666.06 Mbit/s. Due to round off errors, this leads to a slightly different value for k than in the example. Example 3: A Fibre Channel link has a bit rate of 1062.50 Mbit/s and consequently fits in octave number 1, so M = 2. Suppose the reference frequency provided at pins CREF(Q) is 19.44 MHz. This means that the reference division R needs to be 1. The values of n and k can be calculated from the flowchart: bit rate x M x R 1062.50 Mbits x 2 x 1 n.k = --------------------------------------- = -------------------------------------------------------- = 109.3106996 f ref 19.44 MHz This means that n = 109, k = 0.3107 and bit RXNILFRAC should be logic 0 (register C3h). Since k is between 0.25 and 0.75, k does not need to be corrected and N = 2 x n = 218. Consequently the appropriate values are: R = 1 (register A1h), M = 2 (register C0h) and N = 218 (registers C1h and C2h). K = 01 0011 1110 0010 1000 0001 (registers C3h to C5h). Example 4: A non standard transmission link has a bit rate of 3012 Mbit/s and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 20.50 MHz. This means that the reference division R needs to be 1. The values of n and k can be calculated from the flowchart: 3012 Mbits x 1 x 1 bit rate x M x R n.k = --------------------------------------- = ----------------------------------------------- = 146.9268293 20.50 MHz f ref This means that n = 146, k = 0.9268293 and bit RXNILFRAC should be logic 0 (register C3h). Since k is larger than 0.75, k needs to be corrected to 0.4268293 and N = 2 x n + 1 = 293. Consequently the appropriate values are: R = 1 (register A1h), M = 1 (register C0h) and N = 293 (registers C1h and C2h). K = 01 1011 0101 0001 0010 1011 (registers C3h to C5h). If the I2C-bus is not used, the DCR can be set up for the eight pre-programmed bit rates by pins DR0 to DR2 with an applied reference frequency of 19.44 MHz (see Table 3). 2003 Dec 16 14 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Reference clock programming The reference clock, connected to pins CREF(Q), is used for both the DCR frequency window detector and the transmitter synthesizer. The reference clock is divided by divider R. Pre-programmed operating in an SDH/SONET application assumes the use of a reference clock with a frequency that is a multiple (R) of 19.44 MHz. For other applications, any reference frequency between 18 and 21 MHz may be used. If a reference frequency is selected, any bit rate between 30 Mbit/s and 3.2 Gbit/s is supported. The division ratio and reference frequency can be programmed by the bits FREFI2C[2:0] of register REFDIV (A1h) or by pins FREF0 and FREF1. Internally, the reference frequency is always divided to the lowest frequency range between 18 and 21 MHz and for SDH/SONET applications to 19.44 MHz. This is done by divider R which is set by the described pins and bits. In the pre-programmed mode (Table 6) four ranges of clock frequencies can be used by programming R through pins FREF0 and FREF1. In I2C-bus mode (Table 7) two additional ranges of clock frequencies can be used by programming R through bits FREFI2C[2:0]. Table 6 Truth table for reference divider R in pre-programmed mode REFERENCE FREQUENCY RANGE (MHz) 18 to 21 36 to 42 144 to 168 576 to 672 Fig.9 on-chip off-chip TZA3015HW Reference input For optimum jitter performance and Power Supply Rejection Ratio (PSRR), the sensitive reference input should be driven differentially (see Fig.9). If the reference frequency source (fref) is single-ended, the unused CREF or CREFQ input should be terminated with an impedance which matches the source impedance Rsource. The PSRR can be improved by AC coupling the reference frequency source to inputs CREF and CREFQ. Any low frequency noise injected from the fref power supply will be attenuated by the resulting high-pass filter. The low cut-off frequency of the AC coupling must be lower than the reference frequency, otherwise the reference signal will be attenuated and the signal to noise ratio will be reduced. The value of coupling capacitor C is calculated using the 1 formula: C > ---------------------------------2R source f ref handbook, halfpage VCCD VCC 50 50 43 CREF C C DIVISION FACTOR SDH/SONET R FREF1 FREF0 (MHz) HIGH HIGH LOW LOW Table 7 HIGH LOW HIGH LOW 1 2 8 32 19.44 38.88 155.52 622.08 PIN 42 CREFQ Rsource Rsource fref MDB060 Truth table for reference divider R in I2C-bus mode BIT DIVISION FACTOR R 1 2 4 8 16 32 REFERENCE FREQUENCY RANGE (MHz) 18 to 21 36 to 42 72 to 84 144 to 168 288 to 336 576 to 672 15 Reference input with single-ended clock source. FREF I2C2 0 0 0 0 1 1 FREF I2C1 0 0 1 1 0 0 FREF I2C0 0 1 0 1 0 1 Prescaler outputs The prescaler output RXPRSCL(Q) is the VCO frequency of the DCR divided by the main division factor N. It can be used as an accurate reference for another PLL, since it corresponds to the recovered data rate. If needed, the polarity of the prescaler outputs can be inverted by bit RXPRSCLINV of register DDR&RXPRSCL (D5h). If no prescaler information is desired, the output can be disabled by bit RXPRSCLEN of the same register. Apart 2003 Dec 16 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver from these settings, the signal amplitude can be set. This parameter follows the settings of the LVDS outputs. For programming details, see Section "LVDS outputs". TZA3015HW INWINDOW output The status of the FWD circuit is reflected in the state of pin INWINDOW; HIGH for an `in window' situation and LOW whenever the VCO is outside the defined frequency window. Due to the fact that the device enters the frequency acquisition mode when out of window is detected, the INWINDOW pin will have an intermittent value when the input signal is not within the defined window boundary. DEMULTIPLEXER The demultiplexer converts the serial input bit stream to a parallel format. The output data is available on a 4-bit LVDS-bus, thus reducing the data frequency by a factor four. Apart from the de-serializing function, the demultiplexer comprises a parity calculator and a frame header detection circuit. The calculated parity (even) is available at output pins RXPAR(Q), whereas occurrence of the frame header pattern in the data stream results in a one clock cycle (parallel clock output) wide pulse on output pins RXFP(Q). If pin ENBA is HIGH, automatic byte (word) alignment takes place, formatting the parallel output to logical nibbles. Apart from pin ENBA, this mode can be invoked by bits I2CENBA and ENBA of register DMXCON (B8h). To support most commonly used transmission protocols, the frame header pattern can be programmed to any 32-bit pattern (see Section "Frame detection"). If required, the demultiplexer output can be forced into a fixed logic state by bit DMXMUTE of register DMXCON (B8h). The highest supported parallel bus speed is 800 Mbit/s. FWD programming The default width of the window for frequency acquisition is 1000 ppm around the required bit rate. This window size can be changed between 4000 and 250 ppm by bits WINSIZE[2:0] of register DCRCON (C6h). This allows for loose or tight coupling of the VCO to the applied reference clock. Another feature is to define a window width of 0 ppm, by means of pin WINSIZE, see Table 8. This effectively removes the dead zone from the FWD, rendering the FWD into a classical PLL. The VCO will be directly locked to the reference signal instead of the incoming bit stream. Apart from pin WINSIZE, this mode can be invoked by bits I2CWINSIZE and WINSIZE of register DCRCON(C6h). Table 8 Truth table for pin WINSIZE FREQUENCY WINDOW (ppm) 0 1000 WINSIZE LOW HIGH Accurate clock generation during loss of signal A zero window size is especially interesting in the absence of input data, since the frequency of the `recovered clock' will be equal to the programmed line clock rate. Bit AUTOWIN of register DCRCON (C6h) (see Table 9) makes the window size dependent on the LOS status of the limiter. If the optical input signal is lost, the FWD automatically selects the 0 ppm window size; i.e. a direct lock to the reference frequency. This results in a stable and defined output clock during LOS situations, while automatically reverting back to normal DCR operating when the input signal returns. The accuracy of the reference frequency needs to be better than 20 ppm if the application has to comply with ITU-T recommendations. Table 9 Truth table for bit AUTOWIN FREQUENCY WINDOW FWD user defined FWD dependent on LOS Frame detection Byte alignment is enabled if the enable byte alignment input (pin ENBA) is forced HIGH. Whenever a 32-bit sequence matches the programmed header pattern, the incoming data is formatted into logical bytes (being output as nibbles) and a frame pulse is generated on differential output pins RXFP(Q). Any header pattern can be programmed through registers HEADER3 to HEADER0 (B0h to B3h). It is possible to enter a `don't care' for any bit position, e.g. to program a header pattern that is much shorter than 32 bits or to program a pattern with a gap in it. AUTOWIN 0 1 2003 Dec 16 16 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth MSB HEADER bit 31 HEADER3 0 0 0 1 0 1 1 1 0 1 LSB HEADER bit 0 1 0 0 0 1 0 HEADER0 HEADERX3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 HEADERX0 X 0 0 1 0 X 1 1 0 1 1 0 0 0 X X received data data stream MGU548 Fig.10 Example of programming the frame pattern (the symbol `X' represents a don't care). For this, it is necessary to program registers HEADERX3 to HEADERX0 (B4h to B7h). Programming a logic 1 into the HEADERX register will turn the corresponding bit in the HEADER register into a don't care bit, in this way the HEADER register is masked. An example of programming the framing pattern is shown in Fig.10. The default frame header pattern is F6F62828h, corresponding to the middle section of the standard SDH/SONET frame header (the last two A1 bytes plus the first two A2 bytes). If signal ENBA is LOW, no active alignment takes place. However, if the framing pattern happens to occur in the formatted data, a frame pulse will continue to be output on pins RXFP(Q). boundary detection is enabled on the rising edge of ENBA and remains enabled while ENBA is HIGH. Boundaries are recognized on receipt of the second A2 byte and RXFP goes HIGH for one RXPC clock cycle. The four most significant bits of the first A2 byte in the frame header are the first bits that appear on the outgoing data bus (RXPD0 to RXPD3) with the correct alignment. When interfacing with a section terminating device, ENBA must remain HIGH for a full frame after the initial frame pulse. This is to allow the section terminating device to verify internally that frame and byte alignment are correct (see Fig.12). Byte boundary detection is disabled on the first RXFP pulse after ENBA has gone LOW. Figure 13 shows frame and byte boundary detection activated on the rising edge of ENBA and deactivated by the first RXFP pulse after ENBA has gone LOW. Receiver framing in SDH/SONET applications Figure 11 shows a typical SDH/SONET re-frame sequence involving byte alignment. Frame and byte 2003 Dec 16 17 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth serial clock ENBA serial data A1 A1 A1 A2 A2 RXPD0 to RXPD3 invalid data A2, bits 0-3 valid data RXPC RXFP MGU342 Fig.11 Frame and byte detection in SDH/SONET application. handbook, halfpage boundary detection enabled handbook, halfpage ENBA ENBA RXFP RXFP MCE414 boundary detection enabled MCE415 Fig.12 ENBA operating time with section terminating device. Fig.13 Alternate ENBA timing. Receiver framing in other applications In other applications frame headers may be used that are shorter than 32 bits, e.g. 10 bits for Gigabit Ethernet. The position of the frame header in the header register can be chosen freely, but determines the boundary of the parallel data on pins RXPD0(Q) to RXPD3(Q). After alignment, the header bits that are programmed by bits H12 to H15 of register HEADER1 (B2h), appear at the RXPD(Q) outputs. A frame pulse appears at output RXFP(Q) at the same time. Parity generation Outputs RXPAR(Q) provide the even parity of the nibble that is currently available on the parallel bus. With bit RXPARINV of register RXMFOUTC0 (D4h), the parity can be made odd. If no parity check is required, bit RXPAREN of register RXMFOUTC0 (D4h) can be programmed to disable this output, to reduce power dissipation. 2003 Dec 16 18 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Transmitter CLOCK SYNTHESIZER The transmitter frequency can be set independently of the receiver frequency. For this a clock synthesizer is provided that drives the multiplexer. Just like the DCR the clock synthesizer is built around a fractional N synthesizer offering A-rate functionality for the transmit path. The clock synthesizer consists of a VCO, several dividers, a phase frequency detector, an integrated loop filter, a lock detection circuit and a prescaler output buffer (see Fig.14). The internal VCO is phase-locked to the reference clock signal provided at pins CREF(Q). This frequency is internally scaled down (if necessary) to a frequency in the range of 18 to 21 MHz by divider R. TZA3015HW Because of the 22 bits fractional N capability, any combination of bit rate (30 Mbit/s to 3.2 Gbit/s) and reference frequency between 18 and 672 MHz is possible. The LSB (bit k0) of the fractional divider, should be set to logic 1 to avoid limit cycles. These are cycles of less than maximum length, which generate spurs in the frequency spectrum. This leaves bits k[21:1] available for programming the fraction, allowing approximately 10 Hz of frequency resolution without altering the reference frequency. To meet most transmission standards, the reference frequency should be very accurate. In order to be able to synthesize a clean RF clock that is compliant with the most stringent jitter generation requirements, it should also be very clean in terms of phase noise. handbook, full pagewidth LOL OCTAVE DIVIDER up divided CREF(Q) PHASE FREQUENCY DETECTOR down CHARGE PUMP AND LOOP FILTER MAIN DIVIDER N, K TXPRSCL(Q) VCO /M to LM MUX and multiplexer /N MGU682 Fig.14 Schematic diagram of the clock synthesizer. 2003 Dec 16 19 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver All parts of the PLL are internal; no external components are required. This allows for easy application. Programming the clock synthesizer involves four dividers: * Reference divider R * Main divider N * Fractional divider K * Octave divider M. This is essentially the same as for the DCR. The first step is to determine in which octave the desired bit rate fits, see Tables 4 and 5 and Fig.7. Figure 7 shows the position of the most commonly used line rates in relation to the defined octaves of the TZA3015HW. Table 5 clarifies the octave definitions; this yields the value for the octave divider M. The value for R is determined by the reference frequency and the received bit rate (see Section "Reference clock programming"). TZA3015HW Parallel bus clocking schemes The TZA3015HW supports both co-directional and contra-directional clocking schemes for the parallel data bus. The clocking application can be selected by pin CLKDIR or by the bit CLKDIR of register MUXCON0 (F1h). Co-directional clocking is default. Table 10 Truth table for clocking scheme PIN CLKDIR BIT CLKDIR LOW HIGH 0 1 APPLICATION contra-directional clocking co-directional clocking Prescaler output The prescaler output TXPRSCL(Q) is the VCO frequency of the synthesizer divided by the main division factor N. If the synthesizer is in-lock, the frequency is equal to the reference frequency at CREF(Q) divided by R. It can be used as an accurate reference for another PLL. If needed, the polarity of the prescaler outputs can be inverted by bit TXPRSCLINV of register TXMFOUTC (F2h). If no prescaler information is desired, the output can be disabled by bit TXPRSCLEN of the same register. Apart from these settings, the signal amplitude can be set. This parameter follows the settings of the LVDS outputs. For programming details, see Section "LVDS outputs". In the co-directional clocking mode, the parallel clock signal is applied to pins TXPC(Q). The parallel clock signal is generated in the data processing device (e.g. a framer). The co-directional application is depicted in Fig.15. The data processing device may be clocked by an external crystal or by the parallel clock output TXPCO(Q) of the TZA3015HW. This clock output is internally derived from the synthesizer. If the parallel clock output TXPCO(Q) is not required, it can be disabled in order to save dissipation. This is done by programming bit TXPCOEN of register TXMFOUTC (F2h). In a contra-directional clock application, no clock is provided on pin TXPC (see Fig.16). The clock that samples the input data on the parallel bus, is an internal clock derived from signal TXPCO. In this application, the part providing the parallel data has to be clocked with the clock signal TXPCO(Q). In order to alleviate timing problems, the phase of clock TXPCO(Q), with respect to the internal clock, can be shifted in 90 steps. Bit TXPCOINV (180) of register TXMFOUTC (F2h) together with bit TXPOPHASE (90) of register MUXCON0 (F1h) sets the phase shift (see Table 11). Table 11 Truth table for bits TXPCINV and TXPOPHASE TXPCOINV 0 0 1 1 TXPOPHASE 0 1 0 1 PHASE SHIFT 0 90 180 270 Loss of lock During operating, the loss of lock output pin LOL should be LOW which means that the clock synthesizer is in-lock and the output frequency corresponds to the programmed value. If pin LOL goes HIGH, phase and/or frequency lock is lost and the output frequency may deviate from the programmed value. The LOL condition is also available in the registers INTERRUPT (00h) and STATUS (01h). On demand (interrupt is default masked), it generates an interrupt signal at pin INT. MULTIPLEXER The multiplexer comprises a high-speed input register, a 4-stage First In First Out (FIFO) elastic buffer, a parity check circuit and the actual multiplexing tree. 2003 Dec 16 20 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth FRAMER TZA3015HW TXPAR TXPARQ 4 TXPD0 to TXPD3 TXPD0Q to TXPD3Q TXPC TXPCQ TXPCO TXPCOQ FIFORESET CREF TX_PARITY TX_DATA 4 TX_CLK TX_CLK_SRC MGU684 system clock Fig.15 Co-directional clocking diagram. handbook, full pagewidth FRAMER TZA3015HW TXPAR TXPARQ 4 TXPD0 to TXPD3 TXPD0Q to TXPD3Q TX_PARITY TX_DATA 4 TX_CLK_SRC TXPCO TXPCOQ FIFORESET CREF MGU685 system clock Fig.16 Contra-directional clocking diagram. 2003 Dec 16 21 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Double data rate mode Usually the parallel clock frequency (TXPC, RXPC and TXPCO) equals the parallel data rate (for example when the serial bit rate is 2.488 Gbit/s, the parallel bit rate is 622 Mbit/s and the data is clocked with a 622 MHz clock). This is the default operating mode. However, in some applications it is required to use a parallel clock operating at a frequency that is half of the parallel data rate. This is the DDR mode (for example when the serial bit rate is 2.488 Gbit/s, the parallel bit rate is 622 Mbit/s and the data is clocked at both the rising as well as the falling edge of the 311 MHz clock). The timing for the parallel input interface is in accordance with the SFI4 specification. The DDR functionality can be enabled by pin ENDDR (see Table 12) or via the I2C-bus. I2C-bus control is enabled by setting bit I2CDDR of register DDR&RXPRSCL (D5h). In I2C-bus mode the three parallel clocks can be set separately in the DDR mode by bits RXPCDDREN, TXPCDDREN and TXPCODDREN of registers DDR&RXPRSCL (D5h), MUXCON0 (F1h) and TXMFOUTC (F2h) respectively (see Tables 13, 14 and 15). The DDR mode is functional for the whole bit-rate range, so it is true A-rate. Table 12 Truth table for pin ENDDR ENDDR LOW HIGH MODE TXPC, RXPC and TXPCO in normal mode TXPC, RXPC and TXPCO in DDR mode TZA3015HW Table 15 Truth table for bit TXPCODDREN TXPCODDREN 1 0 MODE TXPCO in DDR mode TXPCO in normal mode FIFO register In the co-directional clocking scheme, the input register samples the parallel bus data on the rising edge of the clock signal TXPC(Q). The same clock writes this data into the FIFO register. Data is retrieved from the FIFO by an internal clock, derived from the clock generator of the actual multiplexing tree. This provides for large jitter tolerance on the parallel interface; the FIFO absorbs momentary phase disturbances. Excessively large phase disturbances may stretch the elastic buffer to its limits, causing a FIFO overflow or underflow. Pin OVERFLOW and the registers STATUS (01h) and INTERRUPT (00h) indicate this situation. On demand (i.e to programmed in the register INTMASK [A0h]) it generates an interrupt signal at pin INT. The overflow alarm persists until the FIFO is reset by a HIGH-level on pin FIFORESET or by setting bit FIFORESET of register MUXCON0 (F1h) to logic 1. A FIFORESET also initializes the FIFO. I2C-bus control of the FIFORESET function is obtained by programming bit I2CFIFORES of register MUXCON0 (F1h). To fully benefit from the FIFO, it should be reset whenever there has been a LOL condition, or when bit rates have changed. The asynchronous signal FIFORESET is re-timed by the internal clock from the clock generator. Two clock cycles after signal FIFORESET has been made HIGH, the FIFO initializes. Two clock cycles after signal FIFORESET has been made LOW, the FIFO will be operational again. To initialize automatically, when an overflow has occurred, it is possible to connect pin OVERFLOW to pin FIFORESET directly or via a resistor. Table 13 Truth table for bit RXPCDDREN RXPCDDREN 1 0 MODE RXPC in DDR mode RXPC in normal mode Multiplexing bus swap Bit TXBUSSWAP of register MUXCON1 (F0h) swaps the bus order of the parallel data input bus TXPD0(Q) to TXPD3(Q). Bit TXBUSSWAP reverses the order of bits from MSB to LSB, or vice versa, to allow for optimum connectivity on the PCB. Table 14 Truth table for bit TXPCDDREN TXPCDDREN 1 0 MODE TXPC in DDR mode TXPC in normal mode 2003 Dec 16 22 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Parity checking In order to check the integrity of the data provided on the parallel input bus, a parity checking function has been implemented in the TZA3015HW. The calculated parity, based on the data currently on the bus, is compared to the expected parity provided at pins TXPAR(Q). If these do not match, i.e. a parity error has occurred, the output pins TXPARERR(Q) are HIGH during the next parallel bus clock (TXPC) period. Odd or even parity checking can be selected by pin PAREVEN or by bit TXPAREVEN of register MUXCON1 (F0h). I2C-bus control of the parity type is enabled by setting bit I2CTXPAREVEN of register MUXCON1 (F0h). A HIGH-level on pin PAREVEN corresponds with even parity (default for bit TXPAREVEN), see Table 16. Table 16 Truth table for parity setting LOOP MODES PIN PAREVEN LOW HIGH Jitter performance The clock synthesizer has been optimized for lowest jitter generation and the data and clock recovery has been optimized for the best jitter tolerance. For all SDH/SONET line rates, the jitter tolerance and the jitter generation is compliant with ITU-T standard G.958, provided the reference clock is clean enough. For optimum jitter generation, the single-sideband phase noise of the reference frequency should be less than -140 dBc/Hz, for frequencies greater than 12 kHz from the carrier. If the reference divider R is used, this requirement elevates with approximately 20 x log R. Configuring the main functionality OPERATING MODES The TZA3015HW can be configured in several operating modes. It can be configured as: * Transceiver * Transmitter * Receiver * Transponder with clean-up PLL. The transceiver configuration is the default operating mode. The transmitter and receiver part can be enabled BIT TXPAREVEN 0 1 PARITY TYPE odd even TZA3015HW independently. This saves power when only one half of the functionality is needed. The TZA3015HW can also be configured as a clean-up PLL. This is described in the Section "Loop modes". The operating modes can be selected with pins ENRX and ENTX, these pins enable the receiver and the transmitter. This also offers the possibility to power-down the complete IC. Operating (or enable) modes are listed in Table 17. Table 17 Truth table for the operating modes ENRX LOW LOW HIGH HIGH ENTX LOW HIGH LOW HIGH OPERATING MODE power-down transmitter receiver transceiver (or transponder) The TZA3015HW supports four loop modes: * Line loop back * Diagnostic loop back * Serial loop timing * Clean-up loop back. Selecting the loop modes The required loop mode can be selected either by pins LM0, LM1 and LM2 or by I2C-bus control. The pin settings for the loop mode selection can be seen in Table 18. Table 18 Loop mode selection; note 1 LM2 LOW LOW LOW HIGH HIGH HIGH Note 1. The loop mode can be also programmed by setting bits LM[2:0] in register LOOPMODE (A3h). LM1 LOW LOW HIGH LOW HIGH HIGH LM0 LOW HIGH LOW HIGH LOW HIGH normal line loop back diagnostic loop back serial loop timing clean-up loop back normal MODE 2003 Dec 16 23 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Line loop back mode This mode feeds back the received serial data to the serial data output together with the recovered serial clock. This allows testing of the serial data path including the optic fibres. The received serial data that is fed back is also available in parallel format at the parallel output bus (see Fig.17). TZA3015HW transmit clock is generated. The parallel output clock signal is recovered from the serial output data. This loop mode is used to test the connection between the transceiver and the data processing unit and the system itself. No external fibre optic connection is needed to test the system (see Fig.18). Serial loop timing mode This mode feeds back the recovered clock to the clock synthesizer in order to run the receiver and transmitter at the same clock frequency (see Fig.19). Diagnostic loop back mode This mode feeds back the parallel input data to the parallel outputs together with a parallel clock. The parallel data is serialized and available at the serial output. Also a serial handbook, full pagewidth serial data serial clock data MULTIPLEXER 4 4 4 parallel data parallel clock clock SYNTHESIZER data DEMULTIPLEXER parallel clock MCE416 DCR serial data 4 4 parallel data LIMITER clock Fig.17 Line loop back mode. handbook, full pagewidth serial data serial clock data MULTIPLEXER 4 4 4 parallel data parallel clock clock SYNTHESIZER data DEMULTIPLEXER parallel clock MCE417 DCR serial data 4 4 parallel data LIMITER clock Fig.18 Diagnostic loop back mode. 2003 Dec 16 24 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth serial data serial clock data MULTIPLEXER 4 4 4 parallel data parallel clock clock SYNTHESIZER data DEMULTIPLEXER parallel clock MCE418 DCR serial data 4 4 parallel data LIMITER clock Fig.19 Serial loop timing mode. Clean-up loop back mode The TZA3015HW can be used in transponder applications. In this application, the transmitter is locked onto the recovered clock from the DCR (RXPRSCL). Without preparations, the jitter transfer of this application is determined by cascading the transfer functions of the DCR and the clock synthesizer. This transfer function is not well controlled and may not meet the required specification in terms of bandwidth and/or jitter peaking. A second drawback is that the jitter generation of the synthesizer is degraded because the frequency reference (i.e. the DCR) is not very clean in terms of phase-noise. To improve both the jitter transfer and jitter generation in transponder applications, an external low-noise reference oscillator is locked onto the DCR recovered clock by means of a small band PLL, i.e. the clean-up PLL. The low-noise oscillator, e.g. a Voltage Controlled Crystal Oscillator (VCXO), acts as the reference for the clock synthesizer. If appropriately designed, the jitter will be dominated by the clean-up PLL. This PLL can be optimized for bandwidth and jitter peaking, while the jitter generation is optimized by choosing the appropriate VCXO. Figure 20 shows a typical clean-up PLL application. For ease of use, all components are integrated in the TZA3015HW, except for the VCXO and the loop filter components. The PLL consists of a phase frequency detector, a charge pump, an external loop filter (R, C1 and C2), a VCXO and a reference divider. The combination of R and C1 is mandatory and will transform the current at the output of the charge pump into a control voltage for the VXCO. Capacitor C2 is optional. The internal clock and data path in the TZA3015HW is clarified in Fig.21. As can be seen in the clean-up application, the received (and transmitted) data is also available in parallel format at the parallel output bus. Two bits are available to ease the design of the clean-up PLL. The loop is designed to work with a VCXO that has a positive gain. That is an increasing voltage on the VCXO control input will increase the output frequency. By means of bit CLUPPLLINV of register REFDIV (A1h) the loop is inverted and will work with VCXOs which have a negative gain. Bit CLUPPLLHG of register REFDIV (A1h) will change the gain of the charge pump. If bit CLUPPLLHG is logic 0, the charge pump current ICP is 100 A. If bit CLUPPLLHG is logic 1, the charge pump current ICP is 1 mA. This eases choosing suitable component values for R and C1. 2003 Dec 16 25 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth external components PHASE FREQUENCY DETECTOR IPUMP C1 I2C bit: CLUPPLLHG R C2 VCXO e.g. Vectron VDSGLA type CREF REFERENCE DIVIDER to synthesizer from DCR CHARGE PUMP I2C bit: CLUPPLLINV MCE419 Fig.20 Clean-up PLL application with the TZA3015HW. handbook, full pagewidth serial data serial clock data MULTIPLEXER 4 4 4 parallel data parallel clock clock SYNTHESIZER data DEMULTIPLEXER parallel clock MCE420 DCR serial data 4 4 parallel data LIMITER clock Fig.21 Clean-up loop back mode. I/O configuration LVDS OUTPUTS Several options exist that allow flexible configuration of the LVDS outputs: output amplitude, signal polarity, bus order, mute and selective enable/disable of various outputs. All these options can be set in the registers MFOBCON (A4h), DMXCON (B8h), RXMFOUTC0 (D4h), DDR&RXPRSCL (D5h) and TXMFOUTC (F2h). Affected by these registers are: * Parallel clock output; pins RXPC(Q) * Parallel data output; pins RXPD0(Q) to RXPD3(Q) * Frame pulse output; pins RXFP(Q) * Parity output; pins RXPAR(Q) * Parity error output; pins TXPARERR(Q) 2003 Dec 16 26 * Transmitter parallel clock output; pins TXPCO(Q) * Prescaler DCR output; pins RXPRSCL(Q) * Prescaler synthesizer output; pins TXPRSCL(Q). The output swing of all LVDS outputs can be set by pin LOWSWING or by programming bit LOWSWING in register MFOBCON (A4h). I2C-bus control is enabled by programming bit I2CLOWSWING in register MFOBCON (A4h). The typical voltage levels are given in Table 19. See also Figs 34 and 35. Table 19 Truth table for pin LOWSWING LOWSWING LOW HIGH LVDS OUTPUT VOLTAGE SWING 500 mV 300 mV Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Parallel clock output Bit RXPCINV of register RXMFOUTC0 (D4h) sets the polarity of the parallel clock output RXPC(Q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. This might resolve a parallel bus timing problem. The parallel clock output can be disabled by programming bit RXPCEN of register RXMFOUTC0 (D4h). TZA3015HW Prescaler DCR output The polarity of the receiver prescaler output RXPRSCL(Q) is set by bit RXPRSCLINV of register DDR&RXPRSCL (D5h). The receiver prescaler output can be disabled by programming bit RXPRSCLEN of register DDR&RXPRSCL (D5h). Prescaler synthesizer output The polarity of the transmitter prescaler output TXPRSCL(Q) is set by bit TXPRSCLINV of register TXMFOUTC (F2h). The transmitter prescaler output can be disabled by programming bit TXPRSCLEN of register TXMFOUTC (F2h). LVDS INPUTS The available LVDS inputs are: * Parallel clock input; pins TXPC(Q) * Parallel data input; pins TXPD0(Q) to TXPD3(Q) * Parity input; pins TXPAR(Q). The differential LVDS inputs can handle any input swing with a minimum of 100 mV (p-p) single-ended. The inputs accept any value between VEE and VCC, i.e. the input buffers are true rail-to-rail. The limiting value of the LVDS input current is 25 mA. A differential hysteresis of 25 mV is implemented; see Fig.33. Parallel data output The parallel output bus data RXPD0(Q) to RXPD3(Q) can be swapped by bit RXBUSSWAP of register DMXCON (B8h). The mute option forces the parallel output bits to a logic 0 state. This is done by programming bit DMXMUTE of register DMXCON (B8h). The polarity of the data RXPD0(Q) to RXPD3(Q) can be set by bit RXPDINV of register RXMFOUTC0 (D4h). The data outputs can be disabled by programming bit RXPDEN of register RXMFOUTC0 (D4h). Frame pulse output The polarity of the frame pulse output RXFP(Q) is set by bit RXFPINV of register RXMFOUTC0 (D4h). The frame pulse output can be disabled by programming bit RXFPEN of register RXMFOUTC0 (D4h). Parity output The polarity of the parity output RXPAR(Q) is set by bit RXPARINV of register RXMFOUTC0 (D4h). The parity output can be disabled by programming bit RXPAREN of register RXMFOUTC0 (D4h). Parallel clock input Bit TXPCINV of register MUXCON1 (F0h) sets the polarity of the parallel clock input TXPC(Q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. This could be used to resolve a parallel bus timing problem. Parity error output The polarity of the parity error output TXPARERR(Q) is set by bit TXPARERRINV of register TXMFOUTC (F2h). The parity error output can be disabled by programming bit TXPARERREN of register TXMFOUTC (F2h). Parallel data input The order of the parallel output bus data TXPD0(Q) to TXPD3(Q) can be programmed by bit TXBUSSWAP of register MUXCON1 (F0h). Bit TXPDINV of register MUXCON1 (F0h) sets the polarity of the parallel data inputs TXPD0(Q) to TXPD3(Q). RF OUTPUTS The serial RF outputs are CML type outputs (see Figs 31 and 32). Several options exist that allow flexible configuration of the RF outputs: output amplitude adjustment, signal polarity, data-clock swap, output termination and selective enable/disable of the clock output. Thus, the TZA3015HW can be configured so that Transmitter parallel clock output Bit TXPCOINV of register TXMFOUTC (F2h) sets the polarity of the parallel clock output TXPCO(Q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. The phase of the clock can be shifted by 90 by programming bit TXPCOPHASE of register MUXCON0 (F1h). The combination of these two bits offers a phase shift range of 0 to 360, adjustable in four steps (step size 90). This might resolve a parallel bus timing problem. The parallel clock output can be disabled by programming bit TXPCOEN of register TXMFOUTC (F2h). 2003 Dec 16 27 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver connectivity problems with other ICs are avoided. Unused outputs can be disabled. These options can be programmed in registers TXRFOUTC1 (F3h) and TXRFOUTC0 (F4h). The following RF outputs are available: * Serial data output; pins TXSD(Q) * Serial clock output; pins TXSC(Q). The RF CML data and clock outputs have an adjustable signal amplitude between 70 and 1100 mV (p-p) single-ended in 16 steps. The amplitude can be programmed by setting bits RFS[3:0] of register TXRFOUTC0 (F4h). The default amplitude is 300 mV (p-p) single-ended. The clock and data outputs can be swapped by programming bit TXSDSCSWAP of register TXRFOUTC1 (F3h). Allowing full flexibility in the PCB design. The data and clock outputs can be DC- or AC-coupled to the laser driver. The TZA3015HW serial RF outputs can be adapted to this for optimal connectivity by appropriately setting bit RFOUTTERMAC of register TXRFOUTC0 (F4h). DC termination is default. REFERENCE CLOCK INPUT TZA3015HW The reference clock CREF(Q) input is shown in Fig.36 RF INPUT The serial data inputs are pins RXSD(Q). These pins are differential CML type serial RF data inputs. There are no special settings for these inputs. CMOS OUTPUTS The CMOS outputs are all used as logic outputs to indicate the status of the TZA3015HW. * Loss of signal output; pin LOS * Frequency window detector output; pin INWINDOW * Interrupt output; pin INT * Loss of lock output; pin LOL * FIFO overflow alarm output; pin OVERFLOW. A LOW state equals the ground potential and a HIGH state equals the supply voltage. The INT output can be configured as CMOS output or as open-drain output (see Sections "Open-drain output" and "Interrupt generation"). The output is configured as open-drain output by default. CMOS INPUTS The CMOS inputs are all used as logic inputs to configure the TZA3015HW: * User interface selection input; pin UI * Data rate selection inputs; pins DR0 to DR2 * Loop mode selection inputs; pins LM0 to LM2 * Enable receiver input; pin ENRX * Enable transmitter input; pin ENTX * Wide and narrow frequency detect window selection input; pin WINSIZE * Enable low LVDS swing output input; pin LOWSWING * Reference frequency selection inputs; pins FREF0 and FREF1 * Enable byte alignment input; pin ENBA * FIFO reset input; pin FIFORESET * Odd or even parity check input; pin PAREVEN * Co-directional or contra-directional clocking selection input; pin CLKDIR * Enable serial clock input; pin ENTXSC. Serial clock output The polarity of the serial clock output TXSC(Q) can be programmed by bit TXSCINV of register TXRFOUTC1 (F3h). The serial clock output can be disabled by setting pin ENTXSC or by programming bit TXSCEN of register TXRFOUTC1 (F3h) (see Table 20). This saves power dissipation in applications where the serial clock is not needed Table 20 Truth table for serial clock enable PIN ENTXSC LOW HIGH BIT ENTXSC 0 1 SERIAL CLOCK disabled enabled In order to control the enabling of the serial clock output by the I2C-bus, bit I2CTXSCEN of register TXRFOUTC1 (F3h) must be programmed. Serial data output The polarity of the serial data output TXSD(Q) can be programmed by bit TXSDINV of register TXRFOUTC1 (F3h). The data output can be disabled by programming bit TXSDEN of register TXRFOUTC1 (F3h). 2003 Dec 16 28 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver The CMOS inputs have an internal pull-up resistance; if the input is left open, a logic HIGH state will be forced internally. In the pre-programmed mode (UI = LOW), pins DR0 to 2 act as regular CMOS inputs. In the I2C-bus mode (UI = HIGH), pins SCL and SDA comply with the I2C-bus interface standard. OPEN-DRAIN OUTPUT The TZA3015HW contains one open-drain interrupt output pin INT. The output type of the interrupt controller can be configured by programming bit INTOUT of register INTCONF (A5h). The output can be configured as a push-pull CMOS output or as an open-drain output. For the open-drain configuration an external pull-up resistor of 3.3 k is recommended. The polarity can be set by programming bit INTPOL of register INTCONF (A5h). INTERRUPT GENERATION The TZA3015HW features a fully configurable interrupt generator. An interrupt signal can be generated in the following events: * Loss Of Signal (LOS) * INWINDOW * Temperature alarm * Loss Of Lock (LOL) * FIFO overflow or underflow. The aforementioned events generate flags which can be read in register STATUS (01h). Each of these flags will generate an interrupt in the INTERRUPT register (00h). If programmed so in the register INTMASK (A0h) the INTERRUPT register bit(s) will generate an interrupt on pin INT. In this mask register each interrupt bit can be masked by writing a logic 0 in the corresponding bit position. The STATUS register shows the present status of the receiver. The INTERRUPT register shows the history of the interrupts and is not affected by the INTMASK register. Bit INTOUT of register INTCONF (A5h) determines the output type of pin INT: standard CMOS output or open-drain output. The latter is the default which provides for multiple receivers sharing a common interrupt signal wire with a 3.3 k pull-up resistor (INT is active LOW in this case). The polarity can be set by programming bit INTPOL of register INTCONF (A5h). The interrupt and status register can be polled by an I2C-bus read action. After the read action on the interrupt register the interrupt register is reset by clearing the TZA3015HW interrupt bits where the `alarm' is no longer present. If the `alarm' is still set, the interrupt bit is not cleared after the read action. If an interrupt bit remains set (and if it is not masked) the INT pin will keep its interrupt condition active; it will not generate a pulse nor a spike. The I2C-bus status register is not reset since it always shows the present status of the receiver. It is important to note that the three reserved bits of the STATUS and INTERRUPT registers can take any value and that they can change during operating. These bits can not be used to obtain information on the status of the IC. Power supply connections Four separate supply domains (VDD, VCCD, VCCO and VCCA) provide isolation between the various functional blocks. Each supply domain should be connected to a common VCC via separate filters. All supply domains should be powered synchronously. All supply pins, including the exposed die pad, must be connected. The die pad should be connected with the lowest inductance possible. Since the die pad is also used as the main ground return of the chip, the connection should have a low DC impedance as well. The voltage supply levels should be in accordance with the values specified in Chapter "Characteristics". All external components should be surface mounted devices, preferably of size 0603 or smaller. The components must be mounted as closely to the IC as possible. I2C-BUS I2C-bus characteristics The I2C-bus is a 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Data transfer may be initiated only when the line is not busy. START AND STOP CONDITIONS Figure 22 shows the definition of the start and stop conditions. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). 2003 Dec 16 29 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver ACKNOWLEDGE Figure 23 shows the definition of an acknowledgement on the I2C-bus. Only one data byte is transferred between the start and stop conditions during a write from the transmitter to the receiver. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. TZA3015HW The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. handbook, full pagewidth SDA SDA SCL S START condition P STOP condition SCL MBC622 Fig.22 Start and stop conditions. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement MBC602 1 2 8 9 Fig.23 (Not) acknowledge condition on the I2C-bus. 2003 Dec 16 30 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver I2C-bus protocol Figure 24 shows the definition of the bytes. If bit R/W = 1 the master reads from the read register, if bit R/W = 0 the master writes to the write register. It is not possible to write and read the same register. WRITE PROTOCOL Figure 25 shows the protocol for writing to one single register. After the start command (S) the transmitter sends the address of the slave device, waits for an acknowledge from the slave, sends the register address, waits for an acknowledge, sends data, waits for an acknowledge from the master followed by a stop condition (P). READ PROTOCOL TZA3015HW Figure 26 shows the protocol for reading from one or more registers. After the start command (S) the receiver sends the address of the slave device, waits for an acknowledge from the transmitter slave, receives data from the slave (slave, TZA3015HW, starts sending data after generating the acknowledge), after receiving the data, the receiver (master) sends an acknowledge, or if finished a not-acknowledge followed by a stop condition (P). handbook, full pagewidth MSB LSB MSB LSB R/W 1 Slave address Register address MCE425 Fig.24 Definition of slave- and register address (= instruction byte); slave and register addresses are 7 bits. handbook, full pagewidth acknowledge from slave R/W MSB S SLAVE ADDRESS acknowledge from slave MSB REGISTER ADDRESS acknowledge from master LSB 0A1 A DATA A P one byte transferred MDB071 Fig.25 Write protocol. handbook, halfpage acknowledge from slave R/W MSB acknowledge from master (1) LSB S SLAVE ADDRESS 1A DATA A/A P n bytes MDB072 (1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. Fig.26 Read protocol. 2003 Dec 16 31 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver I2C-BUS REGISTERS TZA3015HW The TZA3015HW can be programmed via the I2C-bus if pin UI = HIGH or leaving the pin open-circuit. The I2C-bus registers can be accessed via the 2-wire I2C-bus interface using pins SCL and SDA if pin CS = HIGH during read or write actions. The I2C-bus address of the TZA3015HW can be found in Table 2. Table 21 I2C-bus registers ADDRESS (HEX) General part 00 01 A0 A1 A3 A4 A5 Transceiver B0 B1 B2 B3 B4 B5 B6 B7 B8 C0 C1 C2 C3 C4 C5 C6 D0 D1 D2 D3 D4 2003 Dec 16 HEADER3 HEADER2 HEADER1 HEADER0 HEADERX3 HEADERX2 HEADERX1 HEADERX0 DMXCON RXOCTDIV RXMAINDIV1 RXMAINDIV0 RXFRACN2 RXFRACN1 RXFRACN0 DCRCON LIMLOSTH LIMLOSCON LIMSL LIMCON RXMFOUTC0 programmable header; MSB (see Table 29) programmable header (see Table 30) programmable header (see Table 31) programmable header; LSB (see Table 32) programmable header don't care; MSB (see Table 33) programmable header don't care (see Table 34) programmable header don't care (see Table 35) programmable header don't care; LSB (see Table 36) demultiplexer configuration register (see Table 37) DCR octave M divider (see Table 38) VCO frequency N divider (see Table 39) VCO frequency N divider (see Table 40) fractional division (see Table 41) fractional division (see Table 42) fractional division (see Table 43) DCR configuration register (see Table 44) limiter loss threshold limiter loss of signal configuration register (see Table 45) limiter slice level limiter amplifier configuration (see Table 46) disable/invert parallel outputs (see Table 47) 32 1111 0110 1111 0110 0010 1000 0010 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 1000 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 1101 0000 0000 0000 0000 1010 1010 n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. 128 to 511 128 to 511 n.a. n.a. n.a. n.a. 0 to 255 n.a. 0 to 255 n.a. n.a. W W W W W W W W W W W W W W W W W W W W W INTERRUPT STATUS INTMASK REFDIV LOOPMODE MFOBCON INTCONF interrupt register (see Table 22) status register (see Table 23) interrupt mask register (see Table 24) reference divider and clean-up PLL (see Table 25) loop mode and enable register (see Table 26) LVDS output buffer configuration (see Table 27) interrupt output configuration (see Table 28) XXXX XXXX XXXX XXXX 0000 0100 0000 0000 0110 0111 0101 0000 0000 0001 n.a. n.a. n.a. n.a. n.a. n.a. n.a. R R W W W W W NAME FUNCTION DEFAULT RANGE R/W Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver ADDRESS (HEX) D5 NAME FUNCTION DEFAULT 0010 0000 TZA3015HW RANGE n.a. R/W W DDR&RXPRSCL disable/invert parallel outputs (see Table 48) Transmitter part E0 E1 E2 E3 E4 E5 F0 F1 F2 F3 F4 TXOCTDIV TXMAINDIV1 TXMAINDIV 0 TXFRACN2 TXFRACN1 TXFRACN0 MUXCON1 MUXCON0 TXMFOUTC TXRFOUTC1 TXRFOUTC0 synthesizer octave divider (see Table 49) VCO frequency (N divider) (see Table 50) VCO frequency (N divider) (see Table 51) fractional division (see Table 52) fractional division (see Table 53) fractional division (see Table 54) multiplexer configuration byte 1 (see Table 55) multiplexer configuration byte 0 (see Table 56) disable/invert LVDS outputs (see Table 57) disable/invert RF outputs (see Table 58) RF output configuration register (see Table 59) 0000 0000 0000 0001 0000 0000 1000 0000 0000 0000 0000 0000 0110 0010 0000 0010 1010 1000 0100 1011 0000 0011 n.a. 128 to 255 128 to 255 n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. W W W W W W W W W W W Table 22 Register INTERRUPT (address: 00h) BIT 7 6 5 4 3 2 1 0 loss of signal 1 0 1 0 1 0 1 0 x 1 0 x x FIFO overflow or underflow FIFO overflow or underflow occurred FIFO normal operating no signal present signal present INWINDOW frequency out of window frequency in window temperature alarm junction temperature 130 C junction temperature <130 C loss of lock synthesizer out of lock synthesizer out of lock reserved OVERFLOW LOL TALARM INWINDOW PARAMETER DESCRIPTION LOS NAME 2003 Dec 16 33 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 23 Register STATUS (address: 01h) BIT 7 6 5 4 3 2 1 0 loss of signal 1 0 1 0 1 0 1 0 x 1 0 x x FIFO over- or underflow FIFO under- or underflow occurred FIFO normal operating no signal present signal present INWINDOW frequency out of window frequency in window temperature alarm junction temperature 130 C junction temperature <130 C loss of lock synthesizer out of lock synthesizer out of lock PARAMETER DESCRIPTION TZA3015HW NAME LOS INWINDOW TALARM LOL reserved OVERFLOW Table 24 Register INTMASK (address: A0h, default value: 04h) BIT 7 6 5 4 3 2 1 0 mask LOS signal 1 0 1 0 1 0 1 0 x 1 0 0 0 0 0 0 1 0 0 x x mask FIFO overflow or underflow not masked masked; note 1 default value not masked masked; note 1 mask INWINDOW signal not masked masked; note 1 mask temperature alarm not masked masked; note 1 mask LOL signal not masked masked; note 1 reserved MOVERFLOW MLOL MTALARM MINWINDOW PARAMETER DESCRIPTION NAME MLOS 2003 Dec 16 34 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Note to Table 24 1. Signal is not processed by the interrupt controller. Table 25 Register REFDIV (address: A1h, default value: 00h) BIT 7 6 5 4 3 2 1 0 PARAMETER DESCRIPTION TZA3015HW NAME FREFI2C[2:0] reference frequency division ratio divider R; octave selection 0 0 0 0 1 1 1 0 x high gain clean-up PLL 1 0 1 0 1 0 0 0 0 0 0 0 0 0 enable high gain normal gain invert charge pump currents of the clean-up PLL clean-up PLL inverted clean-up PLL normal operating enable clean-up PLL clean-up PLL enabled clean-up PLL disabled (except in clean-up loop back mode) 0 0 1 1 0 0 0 1 0 1 0 1 R=1 R=2 R=4 R=8 R = 16 R = 32 reference frequency division programming by I2C-bus I2CFREF enable I2C-bus programming enable programming by pins reserved CLUPPLLHG CLUPPLLINV CLUPPLLEN default value Table 26 Register LOOPMODE (address: A3h, default value: 67h) BIT 7 6 5 4 3 2 0 0 0 0 1 1 1 1 2003 Dec 16 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 normal mode line loop back mode diagnostic loop back mode reserved reserved serial loop timing mode clean-up loop back mode normal mode 35 PARAMETER DESCRIPTION loop mode selection NAME LM[2:0] Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver BIT 7 6 5 4 3 1 0 x enable receiver 1 0 1 0 1 0 0 1 1 0 0 1 1 1 receiver enabled receiver disabled enable transmitter transmitter enabled transmitter disabled transmitter/receiver enable by I2C-bus enable I2C-bus programming enable programming by pins 2 1 0 PARAMETER DESCRIPTION loop mode programming by I2C-bus enable I2C-bus programming enable programming by pins TZA3015HW NAME I2CLM reserved ENRX ENTX I2CENTRX default value Table 27 Register MFOBCON (address: A4h, default value: 50h) BIT 7 6 5 x 1 0 1 0 0 1 0 1 0 0 0 0 4 x 3 x 2 x 1 x 0 x parallel output voltage swing low swing (300 mV) high swing (500 mV) parallel output voltage swing programming by I2C-bus I2CLOWSWING enable I2C-bus programming enable programming by pins default value PARAMETER DESCRIPTION NAME reserved LOWSWING Table 28 Register INTCONF (address: A5h, default value: 01h) BIT 7 6 5 4 3 2 1 0 1 0 1 0 x 0 x 0 x 0 x 0 x 0 x 0 0 1 inverted normal operating interrupt output configuration push-pull output open drain output reserved default value INTOUT PARAMETER DESCRIPTION interrupt output polarity NAME INTPOL 2003 Dec 16 36 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 29 Register HEADER3 (address: B0h, default value: F6h) BIT 7 x 1 6 x 1 5 x 1 4 x 1 3 x 0 2 x 1 1 x 1 0 x 0 PARAMETER DESCRIPTION programmable header; H31 = MSB TZA3015HW NAME H[31:24] default value Table 30 Register HEADER2 (address: B1h, default value: F6h) BIT 7 x 1 6 x 1 5 x 1 4 x 1 3 x 0 2 x 1 1 x 1 0 x 0 PARAMETER DESCRIPTION programmable header NAME H[23:16] default value Table 31 Register HEADER1 (address: B2h, default value: 28h) BIT 7 x 0 6 x 0 5 x 1 4 x 0 3 x 1 2 x 0 1 x 0 0 x 0 PARAMETER DESCRIPTION programmable header NAME H[15:08] default value Table 32 Register HEADER0 (address: B3h, default value: 28h) BIT 7 x 0 6 x 0 5 x 1 4 x 0 3 x 1 2 x 0 1 x 0 0 x 0 PARAMETER DESCRIPTION programmable header; H00 = LSB NAME H[07:00] default value Table 33 Register HEADERX3 (address: B4h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 PARAMETER DESCRIPTION don't care; HX31 = MSB NAME HX[31:24] default value Table 34 Register HEADERX2 (address: B5h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 don't care PARAMETER DESCRIPTION NAME HX[23:16] default value 2003 Dec 16 37 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 35 Register HEADERX1 (address: B6h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 don't care PARAMETER DESCRIPTION TZA3015HW NAME HX[15:08] default value Table 36 Register HEADERX0 (address: B7h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 PARAMETER DESCRIPTION don't care; HX00 = LSB NAME HX[07:00] default value Table 37 Register DMXCON (address: B8h, default value: 00h) BIT 7 6 5 4 3 x 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 2 x 1 x 0 x parallel bus swapping RXPD0 = MSB; RXPD3 = LSB (swapped) RXPD3 = MSB; RXPD0 = LSB (normal) mute parallel outputs enable mute; parallel outputs forced to logic 0 disable mute enable byte alignment byte alignment enabled byte alignment disabled ENBA programming by I2C-bus enable I2C-bus programming default value enable programming by pins I2CENBA ENBA DMXMUTE PARAMETER DESCRIPTION NAME reserved RXBUSSWAP 2003 Dec 16 38 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 38 Register RXOCTDIV (address: C0h, default value: 00h) BIT 7 6 5 4 3 2 0 0 0 0 1 1 1 x 0 x 0 x 0 x 0 x 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 PARAMETER DESCRIPTION division ratio octave divider M; octave selection M = 1; octave number 0 M = 2; octave number 1 M = 4; octave number 2 M = 8; octave number 3 M = 16; octave number 4 M = 32; octave number 5 M = 64; octave number 6 TZA3015HW NAME RXDIV_M[2:0] reserved default value Table 39 Register RXMAINDIV1 (address: C1h, default value: 01h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 1 0 x PARAMETER DESCRIPTION division ratio divider N; RXN8 = MSB NAME RXN8 reserved default value Table 40 Register RXMAINDIV0 (address: C2h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 PARAMETER DESCRIPTION division ratio divider N; RXN0 = LSB NAME RXN[7:0] default value Table 41 Register RXFRACN2 (address: C3h, default value: 80h) BIT 7 6 x RXNILFRAC control bit (NF) 1 0 1 0 0 0 0 0 0 0 no fractional N functionality fractional N functionality default value 5 x 4 x 3 x 2 x 1 x 0 x PARAMETER DESCRIPTION fractional divider; RXK21 = MSB NAME RXK[21:16] reserved RXNILFRAC 2003 Dec 16 39 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 42 Register RXFRACN1 (address: C4h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 fractional divider PARAMETER DESCRIPTION TZA3015HW NAME RXK[15:8] default value Table 43 Register RXFRACN0 (address: C5h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 PARAMETER DESCRIPTION fractional divider; RXK0 = LSB NAME RXK[7:0] default value Table 44 Register DCRCON (address: C6h, default value: 0Ch) BIT 7 6 5 4 3 2 0 1 1 1 1 1 1 0 0 1 0 1 0 1 0 2000 ppm 1000 ppm 500 ppm 250 ppm manual frequency window size selection window size according to bits WINSIZE[2:0] (default value 1000 ppm); PLL frequency loosely coupled to reference crystal window size is 0 ppm; PLL frequency directly synthesized from reference crystal WINSIZE control bit 1 0 1 0 x 0 x 0 0 0 1 1 0 0 through I2C-bus interface AUTOWIN through external pin WINSIZE automatic frequency window size selection enabled disabled reserved default value I2CWINSIZE WINSIZE PARAMETER DESCRIPTION frequency window size; relative to bit rate NAME WINSIZE[2:0] 0 Table 45 Register LIMLOSCON (address: D1h, default value: 0Dh) BIT 7 6 5 4 3 2 1 0 1 0 PARAMETER DESCRIPTION enable loss of signal detection LOS detection enabled LOS detection disabled NAME LOSEN 2003 Dec 16 40 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver BIT 7 6 5 4 3 2 1 1 0 0 PARAMETER DESCRIPTION LOS threshold level programming by I2C-bus enable I2C-bus programming; set level by register D0h TZA3015HW NAME I2CLOSTH set level by applying analog reference voltage on pin LOSTH loss of signal detection hysteresis HTLCB[2:0] 0 dB 1 dB 2 dB 3 dB 4 dB 5 dB 6 dB 7 dB enable slice level SLEN slice level enabled slice level disabled slice level sign SLSGN positive slice level negative slice level LOS level polarity LOSPOL inverted polarity normal polarity 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 1 default value Table 46 Register LIMCON (address: D3h, default value: 00h) BIT 7 6 5 4 3 2 0 0 0 0 1 x 0 x 0 x 0 x 0 x 0 0 0 0 1 0 0 1 1 X 0 0 1 0 1 X PARAMETER DESCRIPTION amplifier octave selection octave number 0; 1800 to 3200 Mbit/s octave number 1; 900 to 1800 Mbit/s octave number 2; 450 to 900 Mbit/s octave number 3; 225 to 450 Mbit/s octave number 4; 30 to 225 Mbit/s reserved default value NAME AMP[2:0] 2003 Dec 16 41 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 47 Register RXMFOUTC0 (address: D4h, default value: AAh) BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 inverted normal parallel data output enable enabled disabled parallel clock output polarity inverted normal parallel clock output enable enabled disabled parity output polarity inverted normal parity output enable enabled disabled frame pulse output polarity inverted normal frame pulse output enable enabled disabled PARAMETER DESCRIPTION parallel data output polarity TZA3015HW NAME RXPDINV RXPDEN RXPCINV RXPCEN RXPARINV RXPAREN RXFPINV RXFPEN default value Table 48 Register DDR&RXPRSCL (address: D5h, default value: 20h) BIT 7 6 5 4 3 x 1 0 1 0 2 x 1 x 0 x invert RX prescaler output inverted normal enable RX prescaler output enabled disabled RXPRSCLEN PARAMETER DESCRIPTION NAME reserved RXPRSCLINV 2003 Dec 16 42 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver BIT 7 6 1 0 1 0 0 0 1 0 0 0 0 0 5 4 3 2 1 0 PARAMETER DESCRIPTION DDR clock frequency mode for RXPC DDR mode enabled normal operating mode DDR programming by I2C-bus enable I2C-bus programming enable programming by pin ENDDR TZA3015HW NAME RXPCDDREN I2CDDR default value Table 49 Register TXOCTDIV (address: E0h, default value: 00h) BIT 7 6 5 4 3 2 0 0 0 0 1 1 1 x 0 x 0 x 0 x 0 x 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 PARAMETER DESCRIPTION division ratio octave divider M; octave selection M = 1; octave number 0 M = 2; octave number 1 M = 4; octave number 2 M = 8; octave number 3 M = 16; octave number 4 M = 32; octave number 5 M = 64; octave number 6 reserved default value NAME TXDIV_M[2:0] Table 50 Register TXMAINDIV1 (address: E1h, default value: 01h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 1 0 x PARAMETER DESCRIPTION division ratio divider N; TXN8 = MSB TXN8 reserved default value NAME Table 51 Register TXMAINDIV0 (address: E2h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 PARAMETER DESCRIPTION division ratio divider N; TXN0 = LSB NAME TXN[7:0] default value 2003 Dec 16 43 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 52 Register TXFRACN2 (address: E3h, default value: 80h) BIT 7 6 x TXNILFRAC control bit (NF) 1 0 1 0 0 0 0 0 0 0 no fractional N functionality fractional N functionality 5 x 4 x 3 x 2 x 1 x 0 x PARAMETER DESCRIPTION fractional divider: TXK21 = MSB TZA3015HW NAME TXK[21:16] reserved TXNILFRAC default value Table 53 Register TXFRACN1 (address: E4h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 fractional divider PARAMETER DESCRIPTION NAME TXK[15:8] default value Table 54 Register TXFRACN0 (address: E5h, default value: 00h) BIT 7 x 0 6 x 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 PARAMETER DESCRIPTION fractional divider; TXK0 = LSB NAME TXK[7:0] default value Table 55 Register MUXCON1 (address: F0h, default value: 62h) BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 PARAMETER DESCRIPTION parallel INPUT bus swapping TXPD0 = MSB; TXPD3 = LSB (swapped) TXPD3 = MSB; TXPD0 = LSB (normal) parity polarity even parity odd parity parity programming by I2C-bus by I2C-bus interface TXPCINV by external pin PAREVEN parallel clock input polarity inverted normal I2CTXPAREVEN TXPAREVEN NAME TXBUSSWAP 2003 Dec 16 44 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver BIT 7 6 5 4 1 0 x 0 x 1 x 1 0 0 0 1 0 3 2 1 0 inverted normal PARAMETER DESCRIPTION parallel data input polarity TZA3015HW NAME TXPDINV reserved default value Table 56 Register MUXCON0 (address: F1h, default value: 02h) BIT 7 6 5 4 3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 x 0 x 0 0 0 0 0 1 0 90 phase shift 0 phase shift parallel clock direction co-directional clocking contra-directional clocking parallel clock direction programming I2C-bus by I2C-bus interface FIFORESET by external pin CLKDIR FIFO reset reset FIFO normal mode FIFO reset programming by I2C-bus by I2C-bus interface TXPCDDREN by external pin FIFORESET DDR clock frequency mode for TXPC DDR mode enabled normal mode reserved default value I2CFIFORES I2CLKDIR CLKDIR PARAMETER DESCRIPTION parallel clock output phase NAME TXPCOPHASE 2003 Dec 16 45 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Table 57 Register TXMFOUTC (address: F2h, default value: A8h) BIT 7 6 5 4 3 2 1 0 x DDR clock frequency mode for TXPCO 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 DDR mode enabled normal mode parallel clock output polarity inverted normal parallel clock output enable enabled disabled prescaler output polarity inverted normal prescaler output enable enabled disabled parity error output polarity inverted normal parity error output enable enabled disabled PARAMETER DESCRIPTION TZA3015HW NAME reserved TXPCODDREN TXPCOINV TXPCOEN TXPRSCLINV TXPRSCLEN TXPARERRINV TXPARERREN default value Table 58 Register TXRFOUTC1 (address: F3h, default value: 4Bh) BIT 7 6 5 4 3 2 1 x 1 0 1 0 1 0 0 x serial output data polarity inverted normal enable serial data output enabled disabled clock and data output swap swapped clock and data output normal clock and data output TXSDSCSWAP TXSDEN PARAMETER DESCRIPTION NAME reserved TXSDINV 2003 Dec 16 46 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver BIT 7 6 5 1 0 1 0 1 0 0 1 0 0 1 0 1 1 4 3 2 1 0 inverted normal enable serial clock output enabled disabled PARAMETER DESCRIPTION serial clock output polarity TZA3015HW NAME TXSCINV TXSCEN serial clock output enable programming by I2C-bus I2CTXSCEN by I2C-bus interface by external pin TXSC default value Table 59 Register TXRFOUTC0 (address: F4h, default value: 03h) BIT 7 6 5 4 3 0 0 1 x 1 0 x 0 0 0 0 0 0 1 1 x serial output termination AC-coupled DC-coupled reserved default value 2 0 0 1 1 0 1 1 0 0 1 1 PARAMETER DESCRIPTION serial output signal amplitude minimum; 70 mV (p-p) default; 300 mV (p-p) maximum; 1100 mV (p-p) reserved RFOUTTERMAC NAME RFS[3:0] 2003 Dec 16 47 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCC VDD Vn analog supply voltage digital supply voltage DC voltage on pins RXPC(Q), RXPD0(Q) to RXPD3(Q), RXFP(Q), RXPAR(Q), TXPARERR(Q), TXPCO(Q), RXPRSCL(Q) and TXPRSCL(Q) 0.7 PARAMETER MIN. -0.5 -0.5 TZA3015HW MAX. +3.6 +3.6 V V UNIT VCC + 0.5 V on pins RXSD(Q), CREF(Q), TXPC(Q), TXPD0(Q) to TXPD3(Q), -0.5 TXPAR(Q), UI, RREF, LOSTH, RSSI, LOS, CS, SDA, SCL, LM0 to LM2, INT, ENRX, ENTX, WINSIZE, INWINDOW, ENDDR, LOWSWING, ENBA, PAREVEN, OVERFLOW, FIFORESET, ENTXSC, TXSD(Q), TXSC(Q), LOL, FREF0, FREF1, CLKDIR and IPUMP In input current on pins RXPC(Q), RXPD0(Q) to RXPD3(Q), RXFP(Q), RXPAR(Q), TXPARERR(Q), TXPCO(Q), RXPRSCL(Q) and TXPRSCL(Q) on pins RXSD(Q) and CREF(Q) on pin INT on pins TXPC(Q), TXPD0(Q) to TXPD3(Q) and TXPAR(Q) Tamb Tj Tstg ambient temperature junction temperature storage temperature -20 VCC + 0.5 V +20 mA -30 -2 -25 -40 - -65 +30 +2 +25 +85 125 +150 mA mA mA C C C THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Notes 1. In compliance with JEDEC standards JESD51-5 and JESD51-7. 2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the PCB. PARAMETER thermal resistance from junction to ambient CONDITIONS notes 1 and 2 VALUE 16 UNIT K/W 2003 Dec 16 48 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW CHARACTERISTICS VCCA = VCCD = VCCO = 3.14 to 3.46 V; Tamb = -40 to +85 C; Rth(j-a) < 16 K/W; all characteristics are specified for the default test settings (see Table 60); all voltages are referenced to VEE; positive currents flow into the device; unless otherwise specified. SYMBOL Supplies ICCA ICCD IDD ICCO ICC(tot) Ptot analog supply current digital supply current digital supply current supply current for clock generator total supply current total power dissipation notes 1 and 2 notes 1 and 2 notes 1 and 2 13 350 0 41 404 1.3 21 395 0.3 55 471 1.6 29 456 1 64 550 1.8 mA mA mA mA mA W PARAMETER CONDITIONS MIN. TYP. MAX. UNIT CMOS inputs: pins UI, CS, DR0 to DR2, LM0 to LM2, ENRX, ENTX, PAREVEN, WINSIZE, LOWSWING, FREF0, FREF1, ENBA, FIFORESET, CLKDIR, ENTXSC and ENDDR VIL VIH IIL IIH LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current VIL = 0 V VIH = VCC - 0.8VCC -200 - - - - - 0.2VCC - - 10 V V A A CMOS outputs: pins LOS, INT, INWINDOW, LOL and OVERFLOW VOL VOH LOW-level output voltage IOL = 1 mA 0 VCC - 0.2 - - 0.2 VCC V V HIGH-level output IOH = -0.5 mA voltage Open-drain output: pin INT VOL IOH LOW-level output voltage IOL = 1 mA 0 - - - 0.2 10 V A HIGH-level output VOH = VCC current single-ended with 50 external load; DC swing; note 3 Serial outputs: pins TXSD(Q) and TXSC(Q) Vo(p-p) default output voltage swing (peak-to-peak value) rise time 220 300 380 mV Zo tr 2003 Dec 16 output impedance single-ended to VCC 20% to 80% 49 40 - 50 60 60 90 ps Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver SYMBOL tf tD-C fbit Vi(p-p) PARAMETER fall time data-to-clock delay duty cycle signal TXSC(Q) output bit rate CONDITIONS 80% to 20% between differential crossovers; see Fig.27 between differential crossovers - -50 40 30 MIN. 60 - 50 - - TYP. 90 TZA3015HW MAX. +50 60 3200 UNIT ps ps % Mbit/s Serial input: pins RXSD(Q) input voltage swing (peak-to-peak value) input voltage sensitivity (peak-to-peak value) typical slice level range input impedance input data rate single-ended; note 4; PRBS (27 - 1) 12 500 mV Vi(sens)(p-p) single-ended; PRBS (27 - 1) - 5 12 mV Vsl Zi fbit note 5 differential -50 80 30 - 100 - +50 120 3200 mV Mbit/s LVDS outputs: pins RXPD0(Q) to RXPD3(Q), RXPC(Q), RXPAR(Q), TXPARERR(Q), RXPRSCL(Q),TXPRSCL(Q), RXFP(Q) and TXPCO(Q) Vo(dif) differential output voltage RL = 100 ; DC-coupled low swing mode, DC high swing mode, DC Vo(cm) tr, tf tD-C RX TX skew common mode output voltage rise and fall time data to clock delay duty cycle RXPC(Q) duty cycle TXPCO(Q) channel to channel skew RL = 100 , DC-coupled CL = 1 pF DDR mode; see Fig.28 normal mode DDR mode normal mode DDR mode RXPD0 to RXPD3, RXPAR and RXFP; note 6 250 400 1.10 100 1/ 4Tclk 300 500 1.22 200 - - 250 1/ 4Tclk 360 600 1.33 250 +200 - 50 1/ 4Tclk mV mV V ps ps + 150 ps % % % % ps normal mode; see Fig.28 -200 45 47 45 47 - 50 50 50 50 - 55 53 55 53 100 LVDS inputs: pins TXPD0(Q) to TXPD3(Q), TXPAR(Q) and TXPC(Q) Vi Vi(th)(dif) input voltage range differential input voltage threshold DC 0 -100 - - VCC +100 mV mV 2003 Dec 16 50 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver SYMBOL Vi(p-p) PARAMETER input voltage swing (peak-to-peak value) differential hysteresis input voltage differential input impedance hold time co-directional clocking set-up time co-directional clocking hold time contradirectional clocking set-up time contra-directional clocking hold time co-directional clocking in DDR mode set-up time co-directional clocking in DDR mode hold time contra-directional clocking in DDR mode see Fig.29 CONDITIONS single-ended; note 6 - MIN. - TYP. TZA3015HW MAX. 1000 UNIT mV Vi(hys) Tamb = 0 C to 85 C Tamb = -40 C to 0 C 25 15 80 - - - 100 150 - - 120 300 mV mV ps zi(dif) th(co) tsu(co) see Fig.29 - 20 300 ps th(contra) see Fig.29 - -1100 -850 ps tsu(contra) see Fig.29 - 1300 1450 ps th(co)DDR fbit = 124 to 800 Mbit/s; see Fig.29 fbit = 30 to 124 Mbit/s; see Fig.29; note 6 fbit = 124 to 800 Mbit/s; see Fig.29 fbit = 30 to 124 Mbit/s; see Fig.29; note 6 see Fig.29 - - - - - 0.3Tclk + 40 4780 -1/4Tclk - 130 -4560 0.3Tclk + 240 5000 -1/4Tclk + 200 -3700 ps ps ps ps tsu(co)DDR th(contra)DDR -1/4Tclk - 1200 -1/4Tclk - 1000 ps tsu(contra)DDR set-up time contra-directional clocking in DDR mode duty cycle clock TXPC(Q) see Fig.29 - 1/ 4Tclk + 1400 1/ 4Tclk + 1600 ps note 6 40 50 60 % Reference frequency input; pins CREF(Q) Vi(p-p) input swing (peak-to-peak value) input voltage range input impedance single-ended 50 - 1000 mV Vi Zi 2003 Dec 16 note 6 single-ended to VCC 51 VCC - 1 40 - 50 VCC + 0.25 60 V Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver SYMBOL fCREF PARAMETER reference clock frequency accuracy reference clock frequency CONDITIONS SDH/SONET requirement see Section "Reference clock programming"; R = 1, 2, 4, 8, 16 or 32 -20 MIN. - TYP. TZA3015HW MAX. +20 UNIT ppm fCREF 18 x R 19.44 x R 21 x R MHz Reference voltage; pin RREF Vref Vi(p-p) reference voltage 10 k resistor to VEE single-ended 1.17 1.21 - 1.26 V Received signal strength indicator; pin RSSI detectable input voltage swing on serial data input (peak-to-peak value) RSSI sensitivity output voltage 5 500 mV SRSSI VRSSI(32mV) see Fig.4 serial data input voltage Vi = 32 mV; PRBS(231 - 1) input 30 to 3200 Mbit/s; PRBS(231 - 1); VCC = 3.14 to 3.47 V; T = 120 C 15 580 17 680 20 780 mV/dB mV Vo output voltage variation -50 - +50 mV Zo Io(source) Io(sink) output impedance output source current output sink current - - - 1 - - 10 1 0.4 mA mA LOS detector hys ta td Icp(source) Icp(sink) hysteresis assert time de-assert time note 7 Vi(p-p) = 3 dB Vi(p-p) = 3 dB CLUPPLLHG = 0 CLUPPLLHG = 1 - - - - - - - 3 - - -0.1 -1 0.1 1 - 5 5 - - - - dB s s mA mA mA mA Clean-up PLL: pin IPUMP charge pump source current charge pump sink CLUPPLLHG = 0 current CLUPPLLHG = 1 2003 Dec 16 52 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver SYMBOL PARAMETER CONDITIONS MIN. TYP. TZA3015HW MAX. UNIT Jitter characteristics Jtol(p-p) jitter tolerance to serial data input signal (peak-to-peak value) STM1/OC3 mode; PRBS(223 - 1) f = 6.5 kHz f = 65 kHz f = 1 MHz STM4/OC12 mode; PRBS(223 - 1) f = 25 kHz f = 250 kHz f = 5 MHz STM16/OC48 mode; PRBS(223 - 1) f = 100 kHz f = 1 MHz f = 20 MHz Jgen(p-p) jitter generation at STM1/OC3 mode; serial data and notes 8 and 9 clock output f = 500 Hz to 1.3 MHz (peak-to-peak f = 12 kHz to 1.3 MHz value) f = 65 kHz to 1.3 MHz STM4/OC12 mode; notes 8 and 9 f = 1 kHz to 5 MHz f = 12 kHz to 5 MHz f = 250 kHz to 5 MHz STM16/OC48 mode; note 8 f = 5 kHz to 20 MHz f = 12 kHz to 20 MHz f = 1 MHz to 20 MHz PLL characteristics receiver tacq tacq(pc) tacq(o) acquisition time 30 Mbit/s; note 6 - - - - - - 200 10 10 s ms s acquisition time at 30 Mbit/s; note 6 power cycle acquisition time octave change 30 Mbit/s; note 6 - - - 32 30 6 250 50 50 mUI mUI mUI - - - - - - 63 13 13 mUI mUI mUI 3 0.3 0.3 10 1 0.5 - - - UI UI UI 3 0.3 0.3 >10 >1 >0.5 - - - UI UI UI 3 0.3 0.3 >10 >1 >0.5 - - - UI UI UI - - - - - - 16 4 4 mUI mUI mUI I2C-bus input and output: pins SCL and SDA VIL VIH LOW-level input voltage HIGH-level input voltage 53 - 0.8VCC - - 0.2VCC - V V 2003 Dec 16 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver SYMBOL Vhys PARAMETER hysteresis of Schmitt-trigger inputs LOW-level output voltage on pin SDA (open-drain) input leakage current input capacitance note 6 CONDITIONS note 6 MIN. 0.05VCC - TYP. - TZA3015HW MAX. UNIT V VOL IOL = 3 mA 0 - 0.4 V ILI Ci -10 - - 1.3 0.6 0.6 0.6 0 100 0.6 20 20 1.3 - - - - - - - - - - - - - +10 10 A pF I2C-bus timing; note 6 fSCL tLOW tHD;STA tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tr tf tBUF SCL clock frequency SCL LOW time hold time START condition SCL HIGH time set-up time START condition data hold time data set-up time set-up time STOP condition SCL and SDA rise time SCL and SDA fall time bus free time between STOP and START capacitive load for each bus line pulse width of allowable spikes noise margin at LOW-level noise margin at HIGH-level 100 - - - - 0.9 - - 300 300 - kHz s s s s s ns s ns ns s Cb tSP VnL VnH Notes - 0 0.1VCC 0.2VCC - - - - 400 50 - - pF ns V V 1. For the typical specification LVDS outputs: RXPAR(Q), RXPRSCL(Q), TXPARERR(Q), TXPCO(Q) and TXPRSCL(Q) are disabled. Also serial output TXSC(Q) is disabled. 2. The following conditions are valid for the maximum specification and are additional to the default settings: bit CLUPPLLEN = 1 (clean-up PLL is enabled); bit CLUPPLLHG = 1 (high gain); line loop back is enabled; pin LOWSWING = LOW (high swing for LVDS outputs); bits RFS[3:0] = 1111 (maximum output swing for TXSD(Q) and 2003 Dec 16 54 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW TXSC(Q). These maximum settings yield the following maximum specification values: ICCD = 680 mA, ICC(tot) = 774 mA and Ptot = 2.7 W. 3. The output swing is adjustable between 70 mV (typical) and 1100 mV (typical) in 16 steps controlled by bits RFS[3:0] of the register TXRFOUTC0 (F4h). 4. The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. 5. The slice level is adjustable in 256 steps controlled by register LIMSL (D2h). 6. Guaranteed by design. 7. The hysteresis is adjustable in 8 steps controlled by bits HTLCB[2:0] of register LIMLOSCON (D1h). 8. Reference frequency of 19.44 MHz, with a phase-noise of less than -140 dBc for frequencies of more than 12 kHz from the carrier (measured during 60 seconds, within the appropriate bandwidth). 9. For bit rates lower than 1.8 Gbit/s, the jitter decreases by the octave division ratio M. Table 60 Default test settings PIN UI = LOW DR0 = LOW, DR1 = HIGH, DR2 = LOW LM0 = HIGH, LM1 = HIGH, LM2 = HIGH ENRX = HIGH ENTX = HIGH ENDDR = LOW LOWSWING = HIGH FREF0 = HIGH, FREF1 = HIGH RREF IPUMP RSSI LOSTH ENTXSC = HIGH WINSIZE = HIGH ENBA = HIGH PAREVEN = HIGH CREF(Q) RXSD(Q) RXPD0(Q) to RXPD3(Q), RXFP(Q), RXPAR(Q), RXPC(Q), TXPCO(Q), TXPARERR(Q), TXPRSCL(Q) and RXPRSCL(Q) TXPC(Q), TXPD0(Q) to TXPD3(Q) and TXPAR FIFORESET = LOW CLKDIR = HIGH TXSD(Q) and TXSC(Q) CMOS outputs pre-programmed mode STM16/OC48 normal mode receiver enabled transmitter enabled DDR mode disabled low LVDS swing 19.44 MHz reference RRREF = 10 k to VEE open circuit open circuit VLOSTH = 0.6 V serial output clock enabled 1000 ppm automatic byte alignment even parity AC-coupled, fi = 19.44 MHz, Vi = 0.2 V (p-p) single-ended input STM16; PRBS (223 - 1) 100 differential outputs SETTING open circuit normal mode co-directional clocking external load of 50 to VCC not loaded 2003 Dec 16 55 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth TXSC t D-C TXSD MGX390 The timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signals are differential). Fig.27 Serial bus output timing. handbook, full pagewidth RXPC t D-C RXPD0 to RXPD3 RXFP, RXPAR MGX478 The timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signals are differential). Fig.28 Parallel bus output timing. handbook, full pagewidth T clk TXPCO, TXPC th t su TXPD0 to TXPD3 valid data MCE422 The timing is measured from the crossover point of the reference signal to the crossover point of the input. Fig.29 Parallel bus co-directional (TXPC) and contra-directional (TXPCO) timing. 2003 Dec 16 56 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver APPLICATION INFORMATION Calculations on the clean-up PLL The important specifications of the clean-up PLL are the bandwidth (f-3dB) and the jitter peaking. If these are known, the component parameters can be calculated. First assume that the bandwidth of the VCXO control input (f-3dB(vcxo)) is much higher than f-3dB and C2 is left out. This simplifies the loop into a second order, type II PLL. In a second order PLL, the damping factor determines the amount of peaking. To obtain peaking of less than 0.1 dB, must be higher than 4.3. For peaking of less than 0.05 dB, must be higher than 6. See Fig.30 for an example. Now R and C1 may be calculated with the following formulas: RDIV x 2 x x f -3dB R = ----------------------------------------------------K VCXO x I CP K VCXO x I CP x C 1 = -----------------------------------------------------2 2 RDIV x x ( f -3dB ) Where: RDIV = reference divider ratio (1, 2, 4, 8, 16 or 32) f-3dB = clean-up PLL bandwidth in Hz KVCXO = VCXO gain in Hz/V ICP = charge pump current in A (100 A or 1 mA, depending on I2C-bus bit CLUPPLLHG) = damping factor. These formulas are valid if: >> 1 and f-3dB(VCXO) > 2 x f-3dB and C1 + C2 --------------------------------------------------- > 2 x f -3dB . 2 x x R x C1 x C2 2 TZA3015HW The transfer has a first order roll-off (i.e. 20 dB/decade), up to the bandwidth of the VCXO control input. If a second order roll-off is required C2 may be added, as long as C1 + C2 ----------------------------------------- > 2 x f -3dB 2 x x C1 x C2 Example: The clean-up PLL uses a VCXO with a frequency of 20 MHz and has a gain KVCXO = 2000 Hz/V. The bandwidth of the control input is f-3dB(VCXO) = 10 kHz. Since the reference frequency is 20 MHz, the reference divider ratio RDIV = 1. According to the specification, the maximum allowed jitter peaking is 0.1 dB. To add some margin the design is for less than 0.05 dB peaking, so = 6. Also according to the specification, f-3dB should be less than 100 kHz. To satisfy the conditions as previously described, f-3 dB < 0.5 x f-3 dB(VCXO) < 5 kHz. To cope with component tolerances, f-3dB(VCXO) = 2.5 kHz is chosen. 1 x 2 x x 2500 R = ----------------------------------------------- = 78540 -6 2000 x 100 x 10 2000 x 100F x 6 C 1 = ------------------------------------------------- = 116.7nF 2 2 1 x x 2500 Choosing ICP = 1 mA yields R = 7854 and C1 = 1.167 F. To calculate f-3dB and , if R and C1 are known, use the following formulas: K VCXO x I CP x R f -3dB = -----------------------------------------2 x x RDIV K VCXO x I CP x C1 R = --- x ---------------------------------------------RDIV 2 2 2003 Dec 16 57 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth Jtransfer [dB] jitter peaking f-3 dB -3 f-3 dB (VCXO) MCE423 log(f) [Hz] 20 dB/decade 40 dB/decade Fig.30 Clean-up PLL jitter transfer. I/O CONFIGURATIONS handbook, full pagewidth SWING CONTROL VCC Vbias 50 transmission lines 50 to highimpedance input 50 50 50 OUT Iswing OUTQ 50 in on-chip off-chip MDB068 Fig.31 Serial RF output (AC-coupled). 2003 Dec 16 58 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth SWING CONTROL VCC 50 50 50 transmission lines 50 50 OUT Iswing OUTQ 50 to highimpedance input in on-chip off-chip MDB069 Fig.32 Serial RF output (DC-coupled). VCCD handbook, halfpage D 50 300 50 DQ 1.8 pF 30 k 30 k VEE MGX391 Fig.33 LVDS input. 2003 Dec 16 59 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth COMMON MODE CONTROL VCC transmission lines OUT 50 Vref OUTQ in 50 MGX392 100 to highimpedance input swing-setting on-chip off-chip Fig.34 LVDS output (DC-coupled). handbook, full pagewidth COMMON MODE CONTROL VCC Vbias AC coupling OUT 50 Vref OUTQ in 50 MGX393 transmission lines 50 50 to highimpedance input swing-setting on-chip off-chip Fig.35 LVDS output (AC-coupled). 2003 Dec 16 60 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver TZA3015HW VCC 50 CREF 50 CREFQ VEE 001aaa056 Fig.36 Reference clock input. 2003 Dec 16 61 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver PACKAGE OUTLINE HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad TZA3015HW SOT638-1 c y exposed die pad side X Dh 75 76 51 50 ZE A e E HE wM bp pin 1 index Lp L detail X Eh A A2 A1 (A3) 100 1 wM ZD 25 bp D HD 26 e vM A B vM B 0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD 10 mm HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 1.15 0.85 1.15 0.85 7 0 16.15 16.15 15.85 15.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 01-03-30 03-04-07 2003 Dec 16 62 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON-T and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Manual soldering TZA3015HW To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2003 Dec 16 63 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7) TZA3015HW SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable not suitable 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. ADDITIONAL SOLDERING INFORMATION The die pad has to be soldered to the PCB for thermal and grounding reasons. 2003 Dec 16 64 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION TZA3015HW This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Dec 16 65 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rateTM 4-bit fibre optic transceiver PURCHASE OF PHILIPS I2C COMPONENTS TZA3015HW Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 Dec 16 66 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R56/04/pp67 Date of release: 2003 Dec 16 Document order number: 9397 750 12216 |
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